1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2019, ARM Limited. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef GIC600_MULTICHIP_H 8*54fd6939SJiyong Park #define GIC600_MULTICHIP_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <stdint.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /* 13*54fd6939SJiyong Park * GIC-600 microarchitecture supports coherent multichip environments containing 14*54fd6939SJiyong Park * up to 16 chips. 15*54fd6939SJiyong Park */ 16*54fd6939SJiyong Park #define GIC600_MAX_MULTICHIP 16 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park /* SPI IDs array consist of min and max ids */ 19*54fd6939SJiyong Park #define GIC600_SPI_IDS_SIZE 2 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park /******************************************************************************* 22*54fd6939SJiyong Park * GIC-600 multichip data structure describes platform specific attributes 23*54fd6939SJiyong Park * related to GIC-600 multichip. Platform port is expected to define these 24*54fd6939SJiyong Park * attributes to initialize the multichip related registers and create 25*54fd6939SJiyong Park * successful connections between the GIC-600s in a multichip system. 26*54fd6939SJiyong Park * 27*54fd6939SJiyong Park * The 'rt_owner_base' field contains the base address of the GIC Distributor 28*54fd6939SJiyong Park * which owns the routing table. 29*54fd6939SJiyong Park * 30*54fd6939SJiyong Park * The 'rt_owner' field contains the chip number which owns the routing table. 31*54fd6939SJiyong Park * Chip number or chip_id starts from 0. 32*54fd6939SJiyong Park * 33*54fd6939SJiyong Park * The 'chip_count' field contains the total number of chips in a multichip 34*54fd6939SJiyong Park * system. This should match the number of entries in 'chip_addrs' and 'spi_ids' 35*54fd6939SJiyong Park * fields. 36*54fd6939SJiyong Park * 37*54fd6939SJiyong Park * The 'chip_addrs' field contains array of chip addresses. These addresses are 38*54fd6939SJiyong Park * implementation specific values. 39*54fd6939SJiyong Park * 40*54fd6939SJiyong Park * The 'spi_ids' field contains array of minimum and maximum SPI interrupt ids 41*54fd6939SJiyong Park * that each chip owns. Note that SPI interrupt ids can range from 32 to 960 and 42*54fd6939SJiyong Park * it should be group of 32 (i.e., SPI minimum and (SPI maximum + 1) should be 43*54fd6939SJiyong Park * a multiple of 32). If a chip doesn't own any SPI interrupts a value of {0, 0} 44*54fd6939SJiyong Park * should be passed. 45*54fd6939SJiyong Park ******************************************************************************/ 46*54fd6939SJiyong Park struct gic600_multichip_data { 47*54fd6939SJiyong Park uintptr_t rt_owner_base; 48*54fd6939SJiyong Park unsigned int rt_owner; 49*54fd6939SJiyong Park unsigned int chip_count; 50*54fd6939SJiyong Park uint64_t chip_addrs[GIC600_MAX_MULTICHIP]; 51*54fd6939SJiyong Park unsigned int spi_ids[GIC600_MAX_MULTICHIP][GIC600_SPI_IDS_SIZE]; 52*54fd6939SJiyong Park }; 53*54fd6939SJiyong Park 54*54fd6939SJiyong Park void gic600_multichip_init(struct gic600_multichip_data *multichip_data); 55*54fd6939SJiyong Park #endif /* GIC600_MULTICHIP_H */ 56