1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef FDT_FIXUP_H 8*54fd6939SJiyong Park #define FDT_FIXUP_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #define INVALID_BASE_ADDR ((uintptr_t)~0UL) 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park int dt_add_psci_node(void *fdt); 13*54fd6939SJiyong Park int dt_add_psci_cpu_enable_methods(void *fdt); 14*54fd6939SJiyong Park int fdt_add_reserved_memory(void *dtb, const char *node_name, 15*54fd6939SJiyong Park uintptr_t base, size_t size); 16*54fd6939SJiyong Park int fdt_add_cpus_node(void *dtb, unsigned int afflv0, 17*54fd6939SJiyong Park unsigned int afflv1, unsigned int afflv2); 18*54fd6939SJiyong Park int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, uintptr_t gicr_base, 19*54fd6939SJiyong Park unsigned int gicr_frame_size); 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park #endif /* FDT_FIXUP_H */ 22