xref: /aosp_15_r20/external/arm-trusted-firmware/fdts/stm32mp15xx-dkx.dtsi (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1*54fd6939SJiyong Park// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2*54fd6939SJiyong Park/*
3*54fd6939SJiyong Park * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
4*54fd6939SJiyong Park * Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park#include <dt-bindings/clock/stm32mp1-clksrc.h>
8*54fd6939SJiyong Park#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
9*54fd6939SJiyong Park
10*54fd6939SJiyong Park/ {
11*54fd6939SJiyong Park	memory@c0000000 {
12*54fd6939SJiyong Park		device_type = "memory";
13*54fd6939SJiyong Park		reg = <0xc0000000 0x20000000>;
14*54fd6939SJiyong Park	};
15*54fd6939SJiyong Park
16*54fd6939SJiyong Park	vin: vin {
17*54fd6939SJiyong Park		compatible = "regulator-fixed";
18*54fd6939SJiyong Park		regulator-name = "vin";
19*54fd6939SJiyong Park		regulator-min-microvolt = <5000000>;
20*54fd6939SJiyong Park		regulator-max-microvolt = <5000000>;
21*54fd6939SJiyong Park		regulator-always-on;
22*54fd6939SJiyong Park	};
23*54fd6939SJiyong Park};
24*54fd6939SJiyong Park
25*54fd6939SJiyong Park&bsec {
26*54fd6939SJiyong Park	board_id: board_id@ec {
27*54fd6939SJiyong Park		reg = <0xec 0x4>;
28*54fd6939SJiyong Park		st,non-secure-otp;
29*54fd6939SJiyong Park	};
30*54fd6939SJiyong Park};
31*54fd6939SJiyong Park
32*54fd6939SJiyong Park&clk_hse {
33*54fd6939SJiyong Park	st,digbypass;
34*54fd6939SJiyong Park};
35*54fd6939SJiyong Park
36*54fd6939SJiyong Park&cpu0{
37*54fd6939SJiyong Park	cpu-supply = <&vddcore>;
38*54fd6939SJiyong Park};
39*54fd6939SJiyong Park
40*54fd6939SJiyong Park&cpu1{
41*54fd6939SJiyong Park	cpu-supply = <&vddcore>;
42*54fd6939SJiyong Park};
43*54fd6939SJiyong Park
44*54fd6939SJiyong Park&hash1 {
45*54fd6939SJiyong Park	status = "okay";
46*54fd6939SJiyong Park};
47*54fd6939SJiyong Park
48*54fd6939SJiyong Park&i2c4 {
49*54fd6939SJiyong Park	pinctrl-names = "default";
50*54fd6939SJiyong Park	pinctrl-0 = <&i2c4_pins_a>;
51*54fd6939SJiyong Park	i2c-scl-rising-time-ns = <185>;
52*54fd6939SJiyong Park	i2c-scl-falling-time-ns = <20>;
53*54fd6939SJiyong Park	clock-frequency = <400000>;
54*54fd6939SJiyong Park	status = "okay";
55*54fd6939SJiyong Park
56*54fd6939SJiyong Park	pmic: stpmic@33 {
57*54fd6939SJiyong Park		compatible = "st,stpmic1";
58*54fd6939SJiyong Park		reg = <0x33>;
59*54fd6939SJiyong Park		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
60*54fd6939SJiyong Park		interrupt-controller;
61*54fd6939SJiyong Park		#interrupt-cells = <2>;
62*54fd6939SJiyong Park		status = "okay";
63*54fd6939SJiyong Park
64*54fd6939SJiyong Park		regulators {
65*54fd6939SJiyong Park			compatible = "st,stpmic1-regulators";
66*54fd6939SJiyong Park			buck1-supply = <&vin>;
67*54fd6939SJiyong Park			buck2-supply = <&vin>;
68*54fd6939SJiyong Park			buck3-supply = <&vin>;
69*54fd6939SJiyong Park			buck4-supply = <&vin>;
70*54fd6939SJiyong Park			ldo1-supply = <&v3v3>;
71*54fd6939SJiyong Park			ldo2-supply = <&vin>;
72*54fd6939SJiyong Park			ldo3-supply = <&vdd_ddr>;
73*54fd6939SJiyong Park			ldo4-supply = <&vin>;
74*54fd6939SJiyong Park			ldo5-supply = <&vin>;
75*54fd6939SJiyong Park			ldo6-supply = <&v3v3>;
76*54fd6939SJiyong Park			vref_ddr-supply = <&vin>;
77*54fd6939SJiyong Park			boost-supply = <&vin>;
78*54fd6939SJiyong Park			pwr_sw1-supply = <&bst_out>;
79*54fd6939SJiyong Park			pwr_sw2-supply = <&bst_out>;
80*54fd6939SJiyong Park
81*54fd6939SJiyong Park			vddcore: buck1 {
82*54fd6939SJiyong Park				regulator-name = "vddcore";
83*54fd6939SJiyong Park				regulator-min-microvolt = <1200000>;
84*54fd6939SJiyong Park				regulator-max-microvolt = <1350000>;
85*54fd6939SJiyong Park				regulator-always-on;
86*54fd6939SJiyong Park				regulator-initial-mode = <0>;
87*54fd6939SJiyong Park				regulator-over-current-protection;
88*54fd6939SJiyong Park			};
89*54fd6939SJiyong Park
90*54fd6939SJiyong Park			vdd_ddr: buck2 {
91*54fd6939SJiyong Park				regulator-name = "vdd_ddr";
92*54fd6939SJiyong Park				regulator-min-microvolt = <1350000>;
93*54fd6939SJiyong Park				regulator-max-microvolt = <1350000>;
94*54fd6939SJiyong Park				regulator-always-on;
95*54fd6939SJiyong Park				regulator-initial-mode = <0>;
96*54fd6939SJiyong Park				regulator-over-current-protection;
97*54fd6939SJiyong Park			};
98*54fd6939SJiyong Park
99*54fd6939SJiyong Park			vdd: buck3 {
100*54fd6939SJiyong Park				regulator-name = "vdd";
101*54fd6939SJiyong Park				regulator-min-microvolt = <3300000>;
102*54fd6939SJiyong Park				regulator-max-microvolt = <3300000>;
103*54fd6939SJiyong Park				regulator-always-on;
104*54fd6939SJiyong Park				st,mask-reset;
105*54fd6939SJiyong Park				regulator-initial-mode = <0>;
106*54fd6939SJiyong Park				regulator-over-current-protection;
107*54fd6939SJiyong Park			};
108*54fd6939SJiyong Park
109*54fd6939SJiyong Park			v3v3: buck4 {
110*54fd6939SJiyong Park				regulator-name = "v3v3";
111*54fd6939SJiyong Park				regulator-min-microvolt = <3300000>;
112*54fd6939SJiyong Park				regulator-max-microvolt = <3300000>;
113*54fd6939SJiyong Park				regulator-always-on;
114*54fd6939SJiyong Park				regulator-over-current-protection;
115*54fd6939SJiyong Park				regulator-initial-mode = <0>;
116*54fd6939SJiyong Park			};
117*54fd6939SJiyong Park
118*54fd6939SJiyong Park			v1v8_audio: ldo1 {
119*54fd6939SJiyong Park				regulator-name = "v1v8_audio";
120*54fd6939SJiyong Park				regulator-min-microvolt = <1800000>;
121*54fd6939SJiyong Park				regulator-max-microvolt = <1800000>;
122*54fd6939SJiyong Park				regulator-always-on;
123*54fd6939SJiyong Park			};
124*54fd6939SJiyong Park
125*54fd6939SJiyong Park			v3v3_hdmi: ldo2 {
126*54fd6939SJiyong Park				regulator-name = "v3v3_hdmi";
127*54fd6939SJiyong Park				regulator-min-microvolt = <3300000>;
128*54fd6939SJiyong Park				regulator-max-microvolt = <3300000>;
129*54fd6939SJiyong Park				regulator-always-on;
130*54fd6939SJiyong Park			};
131*54fd6939SJiyong Park
132*54fd6939SJiyong Park			vtt_ddr: ldo3 {
133*54fd6939SJiyong Park				regulator-name = "vtt_ddr";
134*54fd6939SJiyong Park				regulator-min-microvolt = <500000>;
135*54fd6939SJiyong Park				regulator-max-microvolt = <750000>;
136*54fd6939SJiyong Park				regulator-always-on;
137*54fd6939SJiyong Park				regulator-over-current-protection;
138*54fd6939SJiyong Park			};
139*54fd6939SJiyong Park
140*54fd6939SJiyong Park			vdd_usb: ldo4 {
141*54fd6939SJiyong Park				regulator-name = "vdd_usb";
142*54fd6939SJiyong Park				regulator-min-microvolt = <3300000>;
143*54fd6939SJiyong Park				regulator-max-microvolt = <3300000>;
144*54fd6939SJiyong Park			};
145*54fd6939SJiyong Park
146*54fd6939SJiyong Park			vdda: ldo5 {
147*54fd6939SJiyong Park				regulator-name = "vdda";
148*54fd6939SJiyong Park				regulator-min-microvolt = <2900000>;
149*54fd6939SJiyong Park				regulator-max-microvolt = <2900000>;
150*54fd6939SJiyong Park				regulator-boot-on;
151*54fd6939SJiyong Park			};
152*54fd6939SJiyong Park
153*54fd6939SJiyong Park			v1v2_hdmi: ldo6 {
154*54fd6939SJiyong Park				regulator-name = "v1v2_hdmi";
155*54fd6939SJiyong Park				regulator-min-microvolt = <1200000>;
156*54fd6939SJiyong Park				regulator-max-microvolt = <1200000>;
157*54fd6939SJiyong Park				regulator-always-on;
158*54fd6939SJiyong Park			};
159*54fd6939SJiyong Park
160*54fd6939SJiyong Park			vref_ddr: vref_ddr {
161*54fd6939SJiyong Park				regulator-name = "vref_ddr";
162*54fd6939SJiyong Park				regulator-always-on;
163*54fd6939SJiyong Park				regulator-over-current-protection;
164*54fd6939SJiyong Park			};
165*54fd6939SJiyong Park
166*54fd6939SJiyong Park			bst_out: boost {
167*54fd6939SJiyong Park				regulator-name = "bst_out";
168*54fd6939SJiyong Park			};
169*54fd6939SJiyong Park
170*54fd6939SJiyong Park			vbus_otg: pwr_sw1 {
171*54fd6939SJiyong Park				regulator-name = "vbus_otg";
172*54fd6939SJiyong Park			};
173*54fd6939SJiyong Park
174*54fd6939SJiyong Park			vbus_sw: pwr_sw2 {
175*54fd6939SJiyong Park				regulator-name = "vbus_sw";
176*54fd6939SJiyong Park				regulator-active-discharge = <1>;
177*54fd6939SJiyong Park			};
178*54fd6939SJiyong Park		};
179*54fd6939SJiyong Park	};
180*54fd6939SJiyong Park};
181*54fd6939SJiyong Park
182*54fd6939SJiyong Park&iwdg2 {
183*54fd6939SJiyong Park	timeout-sec = <32>;
184*54fd6939SJiyong Park	status = "okay";
185*54fd6939SJiyong Park	secure-status = "okay";
186*54fd6939SJiyong Park};
187*54fd6939SJiyong Park
188*54fd6939SJiyong Park&pwr_regulators {
189*54fd6939SJiyong Park	vdd-supply = <&vdd>;
190*54fd6939SJiyong Park	vdd_3v3_usbfs-supply = <&vdd_usb>;
191*54fd6939SJiyong Park};
192*54fd6939SJiyong Park
193*54fd6939SJiyong Park&rcc {
194*54fd6939SJiyong Park	secure-status = "disabled";
195*54fd6939SJiyong Park	st,clksrc = <
196*54fd6939SJiyong Park		CLK_MPU_PLL1P
197*54fd6939SJiyong Park		CLK_AXI_PLL2P
198*54fd6939SJiyong Park		CLK_MCU_PLL3P
199*54fd6939SJiyong Park		CLK_PLL12_HSE
200*54fd6939SJiyong Park		CLK_PLL3_HSE
201*54fd6939SJiyong Park		CLK_PLL4_HSE
202*54fd6939SJiyong Park		CLK_RTC_LSE
203*54fd6939SJiyong Park		CLK_MCO1_DISABLED
204*54fd6939SJiyong Park		CLK_MCO2_DISABLED
205*54fd6939SJiyong Park	>;
206*54fd6939SJiyong Park
207*54fd6939SJiyong Park	st,clkdiv = <
208*54fd6939SJiyong Park		1 /*MPU*/
209*54fd6939SJiyong Park		0 /*AXI*/
210*54fd6939SJiyong Park		0 /*MCU*/
211*54fd6939SJiyong Park		1 /*APB1*/
212*54fd6939SJiyong Park		1 /*APB2*/
213*54fd6939SJiyong Park		1 /*APB3*/
214*54fd6939SJiyong Park		1 /*APB4*/
215*54fd6939SJiyong Park		2 /*APB5*/
216*54fd6939SJiyong Park		23 /*RTC*/
217*54fd6939SJiyong Park		0 /*MCO1*/
218*54fd6939SJiyong Park		0 /*MCO2*/
219*54fd6939SJiyong Park	>;
220*54fd6939SJiyong Park
221*54fd6939SJiyong Park	st,pkcs = <
222*54fd6939SJiyong Park		CLK_CKPER_HSE
223*54fd6939SJiyong Park		CLK_FMC_ACLK
224*54fd6939SJiyong Park		CLK_QSPI_ACLK
225*54fd6939SJiyong Park		CLK_ETH_PLL4P
226*54fd6939SJiyong Park		CLK_SDMMC12_PLL4P
227*54fd6939SJiyong Park		CLK_DSI_DSIPLL
228*54fd6939SJiyong Park		CLK_STGEN_HSE
229*54fd6939SJiyong Park		CLK_USBPHY_HSE
230*54fd6939SJiyong Park		CLK_SPI2S1_PLL3Q
231*54fd6939SJiyong Park		CLK_SPI2S23_PLL3Q
232*54fd6939SJiyong Park		CLK_SPI45_HSI
233*54fd6939SJiyong Park		CLK_SPI6_HSI
234*54fd6939SJiyong Park		CLK_I2C46_HSI
235*54fd6939SJiyong Park		CLK_SDMMC3_PLL4P
236*54fd6939SJiyong Park		CLK_USBO_USBPHY
237*54fd6939SJiyong Park		CLK_ADC_CKPER
238*54fd6939SJiyong Park		CLK_CEC_LSE
239*54fd6939SJiyong Park		CLK_I2C12_HSI
240*54fd6939SJiyong Park		CLK_I2C35_HSI
241*54fd6939SJiyong Park		CLK_UART1_HSI
242*54fd6939SJiyong Park		CLK_UART24_HSI
243*54fd6939SJiyong Park		CLK_UART35_HSI
244*54fd6939SJiyong Park		CLK_UART6_HSI
245*54fd6939SJiyong Park		CLK_UART78_HSI
246*54fd6939SJiyong Park		CLK_SPDIF_PLL4P
247*54fd6939SJiyong Park		CLK_FDCAN_PLL4R
248*54fd6939SJiyong Park		CLK_SAI1_PLL3Q
249*54fd6939SJiyong Park		CLK_SAI2_PLL3Q
250*54fd6939SJiyong Park		CLK_SAI3_PLL3Q
251*54fd6939SJiyong Park		CLK_SAI4_PLL3Q
252*54fd6939SJiyong Park		CLK_RNG1_LSI
253*54fd6939SJiyong Park		CLK_RNG2_LSI
254*54fd6939SJiyong Park		CLK_LPTIM1_PCLK1
255*54fd6939SJiyong Park		CLK_LPTIM23_PCLK3
256*54fd6939SJiyong Park		CLK_LPTIM45_LSE
257*54fd6939SJiyong Park	>;
258*54fd6939SJiyong Park
259*54fd6939SJiyong Park	/* VCO = 1300.0 MHz => P = 650 (CPU) */
260*54fd6939SJiyong Park	pll1: st,pll@0 {
261*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
262*54fd6939SJiyong Park		reg = <0>;
263*54fd6939SJiyong Park		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
264*54fd6939SJiyong Park		frac = < 0x800 >;
265*54fd6939SJiyong Park	};
266*54fd6939SJiyong Park
267*54fd6939SJiyong Park	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
268*54fd6939SJiyong Park	pll2: st,pll@1 {
269*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
270*54fd6939SJiyong Park		reg = <1>;
271*54fd6939SJiyong Park		cfg = <2 65 1 0 0 PQR(1,1,1)>;
272*54fd6939SJiyong Park		frac = <0x1400>;
273*54fd6939SJiyong Park	};
274*54fd6939SJiyong Park
275*54fd6939SJiyong Park	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
276*54fd6939SJiyong Park	pll3: st,pll@2 {
277*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
278*54fd6939SJiyong Park		reg = <2>;
279*54fd6939SJiyong Park		cfg = <1 33 1 16 36 PQR(1,1,1)>;
280*54fd6939SJiyong Park		frac = <0x1a04>;
281*54fd6939SJiyong Park	};
282*54fd6939SJiyong Park
283*54fd6939SJiyong Park	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
284*54fd6939SJiyong Park	pll4: st,pll@3 {
285*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
286*54fd6939SJiyong Park		reg = <3>;
287*54fd6939SJiyong Park		cfg = <3 98 5 7 7 PQR(1,1,1)>;
288*54fd6939SJiyong Park	};
289*54fd6939SJiyong Park};
290*54fd6939SJiyong Park
291*54fd6939SJiyong Park&rng1 {
292*54fd6939SJiyong Park	status = "okay";
293*54fd6939SJiyong Park};
294*54fd6939SJiyong Park
295*54fd6939SJiyong Park&rtc {
296*54fd6939SJiyong Park	status = "okay";
297*54fd6939SJiyong Park};
298*54fd6939SJiyong Park
299*54fd6939SJiyong Park&sdmmc1 {
300*54fd6939SJiyong Park	pinctrl-names = "default";
301*54fd6939SJiyong Park	pinctrl-0 = <&sdmmc1_b4_pins_a>;
302*54fd6939SJiyong Park	disable-wp;
303*54fd6939SJiyong Park	st,neg-edge;
304*54fd6939SJiyong Park	bus-width = <4>;
305*54fd6939SJiyong Park	vmmc-supply = <&v3v3>;
306*54fd6939SJiyong Park	status = "okay";
307*54fd6939SJiyong Park};
308*54fd6939SJiyong Park
309*54fd6939SJiyong Park&timers15 {
310*54fd6939SJiyong Park	secure-status = "okay";
311*54fd6939SJiyong Park};
312*54fd6939SJiyong Park
313*54fd6939SJiyong Park&uart4 {
314*54fd6939SJiyong Park	pinctrl-names = "default";
315*54fd6939SJiyong Park	pinctrl-0 = <&uart4_pins_a>;
316*54fd6939SJiyong Park	status = "okay";
317*54fd6939SJiyong Park};
318*54fd6939SJiyong Park
319*54fd6939SJiyong Park&uart7 {
320*54fd6939SJiyong Park	pinctrl-names = "default";
321*54fd6939SJiyong Park	pinctrl-0 = <&uart7_pins_c>;
322*54fd6939SJiyong Park	status = "disabled";
323*54fd6939SJiyong Park};
324*54fd6939SJiyong Park
325*54fd6939SJiyong Park&usart3 {
326*54fd6939SJiyong Park	pinctrl-names = "default";
327*54fd6939SJiyong Park	pinctrl-0 = <&usart3_pins_c>;
328*54fd6939SJiyong Park	uart-has-rtscts;
329*54fd6939SJiyong Park	status = "disabled";
330*54fd6939SJiyong Park};
331*54fd6939SJiyong Park
332*54fd6939SJiyong Park&usbotg_hs {
333*54fd6939SJiyong Park	phys = <&usbphyc_port1 0>;
334*54fd6939SJiyong Park	phy-names = "usb2-phy";
335*54fd6939SJiyong Park	usb-role-switch;
336*54fd6939SJiyong Park	status = "okay";
337*54fd6939SJiyong Park};
338*54fd6939SJiyong Park
339*54fd6939SJiyong Park&usbphyc {
340*54fd6939SJiyong Park	status = "okay";
341*54fd6939SJiyong Park};
342*54fd6939SJiyong Park
343*54fd6939SJiyong Park&usbphyc_port0 {
344*54fd6939SJiyong Park	phy-supply = <&vdd_usb>;
345*54fd6939SJiyong Park};
346*54fd6939SJiyong Park
347*54fd6939SJiyong Park&usbphyc_port1 {
348*54fd6939SJiyong Park	phy-supply = <&vdd_usb>;
349*54fd6939SJiyong Park};
350