1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (C) 2019, STMicroelectronics. All Rights Reserved. 3*54fd6939SJiyong Park * Copyright (C) 2021, Grzegorz Szymaszek. 4*54fd6939SJiyong Park * 5*54fd6939SJiyong Park * SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 6*54fd6939SJiyong Park */ 7*54fd6939SJiyong Park 8*54fd6939SJiyong Park#include "stm32mp157.dtsi" 9*54fd6939SJiyong Park#include "stm32mp15xc.dtsi" 10*54fd6939SJiyong Park#include "stm32mp15-pinctrl.dtsi" 11*54fd6939SJiyong Park#include "stm32mp15xxac-pinctrl.dtsi" 12*54fd6939SJiyong Park#include <dt-bindings/clock/stm32mp1-clksrc.h> 13*54fd6939SJiyong Park#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park/ { 16*54fd6939SJiyong Park memory@c0000000 { 17*54fd6939SJiyong Park device_type = "memory"; 18*54fd6939SJiyong Park reg = <0xc0000000 0x20000000>; 19*54fd6939SJiyong Park }; 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park vin: vin { 22*54fd6939SJiyong Park compatible = "regulator-fixed"; 23*54fd6939SJiyong Park regulator-name = "vin"; 24*54fd6939SJiyong Park regulator-min-microvolt = <5000000>; 25*54fd6939SJiyong Park regulator-max-microvolt = <5000000>; 26*54fd6939SJiyong Park regulator-always-on; 27*54fd6939SJiyong Park }; 28*54fd6939SJiyong Park}; 29*54fd6939SJiyong Park 30*54fd6939SJiyong Park&bsec { 31*54fd6939SJiyong Park board_id: board_id@ec { 32*54fd6939SJiyong Park reg = <0xec 0x4>; 33*54fd6939SJiyong Park st,non-secure-otp; 34*54fd6939SJiyong Park }; 35*54fd6939SJiyong Park}; 36*54fd6939SJiyong Park 37*54fd6939SJiyong Park&clk_hse { 38*54fd6939SJiyong Park st,digbypass; 39*54fd6939SJiyong Park}; 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park&cpu0 { 42*54fd6939SJiyong Park cpu-supply = <&vddcore>; 43*54fd6939SJiyong Park}; 44*54fd6939SJiyong Park 45*54fd6939SJiyong Park&cpu1 { 46*54fd6939SJiyong Park cpu-supply = <&vddcore>; 47*54fd6939SJiyong Park}; 48*54fd6939SJiyong Park 49*54fd6939SJiyong Park&cryp1 { 50*54fd6939SJiyong Park status = "okay"; 51*54fd6939SJiyong Park}; 52*54fd6939SJiyong Park 53*54fd6939SJiyong Park&hash1 { 54*54fd6939SJiyong Park status = "okay"; 55*54fd6939SJiyong Park}; 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park&i2c2 { 58*54fd6939SJiyong Park pinctrl-names = "default"; 59*54fd6939SJiyong Park pinctrl-0 = <&i2c2_pins_a>; 60*54fd6939SJiyong Park clock-frequency = <400000>; 61*54fd6939SJiyong Park i2c-scl-rising-time-ns = <185>; 62*54fd6939SJiyong Park i2c-scl-falling-time-ns = <20>; 63*54fd6939SJiyong Park status = "okay"; 64*54fd6939SJiyong Park 65*54fd6939SJiyong Park pmic: stpmic@33 { 66*54fd6939SJiyong Park compatible = "st,stpmic1"; 67*54fd6939SJiyong Park reg = <0x33>; 68*54fd6939SJiyong Park interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 69*54fd6939SJiyong Park interrupt-controller; 70*54fd6939SJiyong Park #interrupt-cells = <2>; 71*54fd6939SJiyong Park status = "okay"; 72*54fd6939SJiyong Park 73*54fd6939SJiyong Park regulators { 74*54fd6939SJiyong Park compatible = "st,stpmic1-regulators"; 75*54fd6939SJiyong Park buck1-supply = <&vin>; 76*54fd6939SJiyong Park buck2-supply = <&vin>; 77*54fd6939SJiyong Park buck3-supply = <&vin>; 78*54fd6939SJiyong Park buck4-supply = <&vin>; 79*54fd6939SJiyong Park ldo1-supply = <&v3v3>; 80*54fd6939SJiyong Park ldo2-supply = <&vin>; 81*54fd6939SJiyong Park ldo3-supply = <&vdd_ddr>; 82*54fd6939SJiyong Park ldo4-supply = <&vin>; 83*54fd6939SJiyong Park ldo5-supply = <&vin>; 84*54fd6939SJiyong Park ldo6-supply = <&v3v3>; 85*54fd6939SJiyong Park vref_ddr-supply = <&vin>; 86*54fd6939SJiyong Park boost-supply = <&vin>; 87*54fd6939SJiyong Park pwr_sw1-supply = <&bst_out>; 88*54fd6939SJiyong Park pwr_sw2-supply = <&bst_out>; 89*54fd6939SJiyong Park 90*54fd6939SJiyong Park vddcore: buck1 { 91*54fd6939SJiyong Park regulator-name = "vddcore"; 92*54fd6939SJiyong Park regulator-min-microvolt = <1200000>; 93*54fd6939SJiyong Park regulator-max-microvolt = <1350000>; 94*54fd6939SJiyong Park regulator-always-on; 95*54fd6939SJiyong Park regulator-initial-mode = <0>; 96*54fd6939SJiyong Park regulator-over-current-protection; 97*54fd6939SJiyong Park }; 98*54fd6939SJiyong Park 99*54fd6939SJiyong Park vdd_ddr: buck2 { 100*54fd6939SJiyong Park regulator-name = "vdd_ddr"; 101*54fd6939SJiyong Park regulator-min-microvolt = <1350000>; 102*54fd6939SJiyong Park regulator-max-microvolt = <1350000>; 103*54fd6939SJiyong Park regulator-always-on; 104*54fd6939SJiyong Park regulator-initial-mode = <0>; 105*54fd6939SJiyong Park regulator-over-current-protection; 106*54fd6939SJiyong Park }; 107*54fd6939SJiyong Park 108*54fd6939SJiyong Park vdd: buck3 { 109*54fd6939SJiyong Park regulator-name = "vdd"; 110*54fd6939SJiyong Park regulator-min-microvolt = <3300000>; 111*54fd6939SJiyong Park regulator-max-microvolt = <3300000>; 112*54fd6939SJiyong Park regulator-always-on; 113*54fd6939SJiyong Park st,mask-reset; 114*54fd6939SJiyong Park regulator-initial-mode = <0>; 115*54fd6939SJiyong Park regulator-over-current-protection; 116*54fd6939SJiyong Park }; 117*54fd6939SJiyong Park 118*54fd6939SJiyong Park v3v3: buck4 { 119*54fd6939SJiyong Park regulator-name = "v3v3"; 120*54fd6939SJiyong Park regulator-min-microvolt = <3300000>; 121*54fd6939SJiyong Park regulator-max-microvolt = <3300000>; 122*54fd6939SJiyong Park regulator-always-on; 123*54fd6939SJiyong Park regulator-over-current-protection; 124*54fd6939SJiyong Park regulator-initial-mode = <0>; 125*54fd6939SJiyong Park }; 126*54fd6939SJiyong Park 127*54fd6939SJiyong Park v1v8_audio: ldo1 { 128*54fd6939SJiyong Park regulator-name = "v1v8_audio"; 129*54fd6939SJiyong Park regulator-min-microvolt = <1800000>; 130*54fd6939SJiyong Park regulator-max-microvolt = <1800000>; 131*54fd6939SJiyong Park regulator-always-on; 132*54fd6939SJiyong Park }; 133*54fd6939SJiyong Park 134*54fd6939SJiyong Park v3v3_hdmi: ldo2 { 135*54fd6939SJiyong Park regulator-name = "v3v3_hdmi"; 136*54fd6939SJiyong Park regulator-min-microvolt = <3300000>; 137*54fd6939SJiyong Park regulator-max-microvolt = <3300000>; 138*54fd6939SJiyong Park regulator-always-on; 139*54fd6939SJiyong Park }; 140*54fd6939SJiyong Park 141*54fd6939SJiyong Park vtt_ddr: ldo3 { 142*54fd6939SJiyong Park regulator-name = "vtt_ddr"; 143*54fd6939SJiyong Park regulator-min-microvolt = <500000>; 144*54fd6939SJiyong Park regulator-max-microvolt = <750000>; 145*54fd6939SJiyong Park regulator-always-on; 146*54fd6939SJiyong Park regulator-over-current-protection; 147*54fd6939SJiyong Park }; 148*54fd6939SJiyong Park 149*54fd6939SJiyong Park vdd_usb: ldo4 { 150*54fd6939SJiyong Park regulator-name = "vdd_usb"; 151*54fd6939SJiyong Park regulator-min-microvolt = <3300000>; 152*54fd6939SJiyong Park regulator-max-microvolt = <3300000>; 153*54fd6939SJiyong Park regulator-always-on; 154*54fd6939SJiyong Park }; 155*54fd6939SJiyong Park 156*54fd6939SJiyong Park vdda: ldo5 { 157*54fd6939SJiyong Park regulator-name = "vdda"; 158*54fd6939SJiyong Park regulator-min-microvolt = <2900000>; 159*54fd6939SJiyong Park regulator-max-microvolt = <2900000>; 160*54fd6939SJiyong Park regulator-boot-on; 161*54fd6939SJiyong Park }; 162*54fd6939SJiyong Park 163*54fd6939SJiyong Park v1v2_hdmi: ldo6 { 164*54fd6939SJiyong Park regulator-name = "v1v2_hdmi"; 165*54fd6939SJiyong Park regulator-min-microvolt = <1200000>; 166*54fd6939SJiyong Park regulator-max-microvolt = <1200000>; 167*54fd6939SJiyong Park regulator-always-on; 168*54fd6939SJiyong Park }; 169*54fd6939SJiyong Park 170*54fd6939SJiyong Park vref_ddr: vref_ddr { 171*54fd6939SJiyong Park regulator-name = "vref_ddr"; 172*54fd6939SJiyong Park regulator-always-on; 173*54fd6939SJiyong Park regulator-over-current-protection; 174*54fd6939SJiyong Park }; 175*54fd6939SJiyong Park 176*54fd6939SJiyong Park bst_out: boost { 177*54fd6939SJiyong Park regulator-name = "bst_out"; 178*54fd6939SJiyong Park }; 179*54fd6939SJiyong Park 180*54fd6939SJiyong Park vbus_otg: pwr_sw1 { 181*54fd6939SJiyong Park regulator-name = "vbus_otg"; 182*54fd6939SJiyong Park }; 183*54fd6939SJiyong Park 184*54fd6939SJiyong Park vbus_sw: pwr_sw2 { 185*54fd6939SJiyong Park regulator-name = "vbus_sw"; 186*54fd6939SJiyong Park regulator-active-discharge = <1>; 187*54fd6939SJiyong Park }; 188*54fd6939SJiyong Park }; 189*54fd6939SJiyong Park 190*54fd6939SJiyong Park pmic_watchdog: watchdog { 191*54fd6939SJiyong Park compatible = "st,stpmic1-wdt"; 192*54fd6939SJiyong Park status = "disabled"; 193*54fd6939SJiyong Park }; 194*54fd6939SJiyong Park }; 195*54fd6939SJiyong Park}; 196*54fd6939SJiyong Park 197*54fd6939SJiyong Park&iwdg2 { 198*54fd6939SJiyong Park timeout-sec = <32>; 199*54fd6939SJiyong Park status = "okay"; 200*54fd6939SJiyong Park}; 201*54fd6939SJiyong Park 202*54fd6939SJiyong Park&pwr_regulators { 203*54fd6939SJiyong Park vdd-supply = <&vdd>; 204*54fd6939SJiyong Park vdd_3v3_usbfs-supply = <&vdd_usb>; 205*54fd6939SJiyong Park}; 206*54fd6939SJiyong Park 207*54fd6939SJiyong Park&rcc { 208*54fd6939SJiyong Park secure-status = "disabled"; 209*54fd6939SJiyong Park st,clksrc = < 210*54fd6939SJiyong Park CLK_MPU_PLL1P 211*54fd6939SJiyong Park CLK_AXI_PLL2P 212*54fd6939SJiyong Park CLK_MCU_PLL3P 213*54fd6939SJiyong Park CLK_PLL12_HSE 214*54fd6939SJiyong Park CLK_PLL3_HSE 215*54fd6939SJiyong Park CLK_PLL4_HSE 216*54fd6939SJiyong Park CLK_RTC_LSE 217*54fd6939SJiyong Park CLK_MCO1_DISABLED 218*54fd6939SJiyong Park CLK_MCO2_DISABLED 219*54fd6939SJiyong Park >; 220*54fd6939SJiyong Park 221*54fd6939SJiyong Park st,clkdiv = < 222*54fd6939SJiyong Park 1 /*MPU*/ 223*54fd6939SJiyong Park 0 /*AXI*/ 224*54fd6939SJiyong Park 0 /*MCU*/ 225*54fd6939SJiyong Park 1 /*APB1*/ 226*54fd6939SJiyong Park 1 /*APB2*/ 227*54fd6939SJiyong Park 1 /*APB3*/ 228*54fd6939SJiyong Park 1 /*APB4*/ 229*54fd6939SJiyong Park 2 /*APB5*/ 230*54fd6939SJiyong Park 23 /*RTC*/ 231*54fd6939SJiyong Park 0 /*MCO1*/ 232*54fd6939SJiyong Park 0 /*MCO2*/ 233*54fd6939SJiyong Park >; 234*54fd6939SJiyong Park 235*54fd6939SJiyong Park st,pkcs = < 236*54fd6939SJiyong Park CLK_CKPER_HSE 237*54fd6939SJiyong Park CLK_FMC_ACLK 238*54fd6939SJiyong Park CLK_QSPI_ACLK 239*54fd6939SJiyong Park CLK_ETH_PLL4P 240*54fd6939SJiyong Park CLK_SDMMC12_PLL4P 241*54fd6939SJiyong Park CLK_DSI_DSIPLL 242*54fd6939SJiyong Park CLK_STGEN_HSE 243*54fd6939SJiyong Park CLK_USBPHY_HSE 244*54fd6939SJiyong Park CLK_SPI2S1_PLL3Q 245*54fd6939SJiyong Park CLK_SPI2S23_PLL3Q 246*54fd6939SJiyong Park CLK_SPI45_HSI 247*54fd6939SJiyong Park CLK_SPI6_HSI 248*54fd6939SJiyong Park CLK_I2C46_HSI 249*54fd6939SJiyong Park CLK_SDMMC3_PLL4P 250*54fd6939SJiyong Park CLK_USBO_USBPHY 251*54fd6939SJiyong Park CLK_ADC_CKPER 252*54fd6939SJiyong Park CLK_CEC_LSE 253*54fd6939SJiyong Park CLK_I2C12_HSI 254*54fd6939SJiyong Park CLK_I2C35_HSI 255*54fd6939SJiyong Park CLK_UART1_HSI 256*54fd6939SJiyong Park CLK_UART24_HSI 257*54fd6939SJiyong Park CLK_UART35_HSI 258*54fd6939SJiyong Park CLK_UART6_HSI 259*54fd6939SJiyong Park CLK_UART78_HSI 260*54fd6939SJiyong Park CLK_SPDIF_PLL4P 261*54fd6939SJiyong Park CLK_FDCAN_PLL4R 262*54fd6939SJiyong Park CLK_SAI1_PLL3Q 263*54fd6939SJiyong Park CLK_SAI2_PLL3Q 264*54fd6939SJiyong Park CLK_SAI3_PLL3Q 265*54fd6939SJiyong Park CLK_SAI4_PLL3Q 266*54fd6939SJiyong Park CLK_RNG1_LSI 267*54fd6939SJiyong Park CLK_RNG2_LSI 268*54fd6939SJiyong Park CLK_LPTIM1_PCLK1 269*54fd6939SJiyong Park CLK_LPTIM23_PCLK3 270*54fd6939SJiyong Park CLK_LPTIM45_LSE 271*54fd6939SJiyong Park >; 272*54fd6939SJiyong Park 273*54fd6939SJiyong Park /* VCO = 1300.0 MHz => P = 650 (CPU) */ 274*54fd6939SJiyong Park pll1: st,pll@0 { 275*54fd6939SJiyong Park compatible = "st,stm32mp1-pll"; 276*54fd6939SJiyong Park reg = <0>; 277*54fd6939SJiyong Park cfg = <2 80 0 0 0 PQR(1,0,0)>; 278*54fd6939SJiyong Park frac = <0x800>; 279*54fd6939SJiyong Park }; 280*54fd6939SJiyong Park 281*54fd6939SJiyong Park /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 282*54fd6939SJiyong Park pll2: st,pll@1 { 283*54fd6939SJiyong Park compatible = "st,stm32mp1-pll"; 284*54fd6939SJiyong Park reg = <1>; 285*54fd6939SJiyong Park cfg = <2 65 1 0 0 PQR(1,1,1)>; 286*54fd6939SJiyong Park frac = <0x1400>; 287*54fd6939SJiyong Park }; 288*54fd6939SJiyong Park 289*54fd6939SJiyong Park /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 290*54fd6939SJiyong Park pll3: st,pll@2 { 291*54fd6939SJiyong Park compatible = "st,stm32mp1-pll"; 292*54fd6939SJiyong Park reg = <2>; 293*54fd6939SJiyong Park cfg = <1 33 1 16 36 PQR(1,1,1)>; 294*54fd6939SJiyong Park frac = <0x1a04>; 295*54fd6939SJiyong Park }; 296*54fd6939SJiyong Park 297*54fd6939SJiyong Park /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 298*54fd6939SJiyong Park pll4: st,pll@3 { 299*54fd6939SJiyong Park compatible = "st,stm32mp1-pll"; 300*54fd6939SJiyong Park reg = <3>; 301*54fd6939SJiyong Park cfg = <3 98 5 7 7 PQR(1,1,1)>; 302*54fd6939SJiyong Park }; 303*54fd6939SJiyong Park}; 304*54fd6939SJiyong Park 305*54fd6939SJiyong Park&rng1 { 306*54fd6939SJiyong Park status = "okay"; 307*54fd6939SJiyong Park}; 308*54fd6939SJiyong Park 309*54fd6939SJiyong Park&rtc { 310*54fd6939SJiyong Park status = "okay"; 311*54fd6939SJiyong Park}; 312*54fd6939SJiyong Park 313*54fd6939SJiyong Park&sdmmc2 { 314*54fd6939SJiyong Park pinctrl-names = "default"; 315*54fd6939SJiyong Park pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>; 316*54fd6939SJiyong Park non-removable; 317*54fd6939SJiyong Park no-sd; 318*54fd6939SJiyong Park no-sdio; 319*54fd6939SJiyong Park st,neg-edge; 320*54fd6939SJiyong Park bus-width = <8>; 321*54fd6939SJiyong Park vmmc-supply = <&v3v3>; 322*54fd6939SJiyong Park vqmmc-supply = <&vdd>; 323*54fd6939SJiyong Park mmc-ddr-3_3v; 324*54fd6939SJiyong Park status = "okay"; 325*54fd6939SJiyong Park}; 326