xref: /aosp_15_r20/external/arm-trusted-firmware/fdts/stm32mp157c-ed1.dts (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1*54fd6939SJiyong Park// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2*54fd6939SJiyong Park/*
3*54fd6939SJiyong Park * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
4*54fd6939SJiyong Park * Author: Ludovic Barre <[email protected]> for STMicroelectronics.
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park/dts-v1/;
7*54fd6939SJiyong Park
8*54fd6939SJiyong Park#include "stm32mp157.dtsi"
9*54fd6939SJiyong Park#include "stm32mp15xc.dtsi"
10*54fd6939SJiyong Park#include "stm32mp15-pinctrl.dtsi"
11*54fd6939SJiyong Park#include "stm32mp15xxaa-pinctrl.dtsi"
12*54fd6939SJiyong Park#include <dt-bindings/clock/stm32mp1-clksrc.h>
13*54fd6939SJiyong Park#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
14*54fd6939SJiyong Park
15*54fd6939SJiyong Park/ {
16*54fd6939SJiyong Park	model = "STMicroelectronics STM32MP157C eval daughter";
17*54fd6939SJiyong Park	compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
18*54fd6939SJiyong Park
19*54fd6939SJiyong Park	chosen {
20*54fd6939SJiyong Park		stdout-path = "serial0:115200n8";
21*54fd6939SJiyong Park	};
22*54fd6939SJiyong Park
23*54fd6939SJiyong Park	memory@c0000000 {
24*54fd6939SJiyong Park		device_type = "memory";
25*54fd6939SJiyong Park		reg = <0xC0000000 0x40000000>;
26*54fd6939SJiyong Park	};
27*54fd6939SJiyong Park
28*54fd6939SJiyong Park	aliases {
29*54fd6939SJiyong Park		serial0 = &uart4;
30*54fd6939SJiyong Park	};
31*54fd6939SJiyong Park};
32*54fd6939SJiyong Park
33*54fd6939SJiyong Park&bsec {
34*54fd6939SJiyong Park	board_id: board_id@ec {
35*54fd6939SJiyong Park		reg = <0xec 0x4>;
36*54fd6939SJiyong Park		status = "okay";
37*54fd6939SJiyong Park		secure-status = "okay";
38*54fd6939SJiyong Park	};
39*54fd6939SJiyong Park};
40*54fd6939SJiyong Park
41*54fd6939SJiyong Park&clk_hse {
42*54fd6939SJiyong Park	st,digbypass;
43*54fd6939SJiyong Park};
44*54fd6939SJiyong Park
45*54fd6939SJiyong Park&cpu0 {
46*54fd6939SJiyong Park	cpu-supply = <&vddcore>;
47*54fd6939SJiyong Park};
48*54fd6939SJiyong Park
49*54fd6939SJiyong Park&cpu1 {
50*54fd6939SJiyong Park	cpu-supply = <&vddcore>;
51*54fd6939SJiyong Park};
52*54fd6939SJiyong Park
53*54fd6939SJiyong Park&cryp1 {
54*54fd6939SJiyong Park	status = "okay";
55*54fd6939SJiyong Park};
56*54fd6939SJiyong Park
57*54fd6939SJiyong Park&hash1 {
58*54fd6939SJiyong Park	status = "okay";
59*54fd6939SJiyong Park};
60*54fd6939SJiyong Park
61*54fd6939SJiyong Park&i2c4 {
62*54fd6939SJiyong Park	pinctrl-names = "default";
63*54fd6939SJiyong Park	pinctrl-0 = <&i2c4_pins_a>;
64*54fd6939SJiyong Park	i2c-scl-rising-time-ns = <185>;
65*54fd6939SJiyong Park	i2c-scl-falling-time-ns = <20>;
66*54fd6939SJiyong Park	clock-frequency = <400000>;
67*54fd6939SJiyong Park	status = "okay";
68*54fd6939SJiyong Park
69*54fd6939SJiyong Park	pmic: stpmic@33 {
70*54fd6939SJiyong Park		compatible = "st,stpmic1";
71*54fd6939SJiyong Park		reg = <0x33>;
72*54fd6939SJiyong Park		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
73*54fd6939SJiyong Park		interrupt-controller;
74*54fd6939SJiyong Park		#interrupt-cells = <2>;
75*54fd6939SJiyong Park		status = "okay";
76*54fd6939SJiyong Park
77*54fd6939SJiyong Park		regulators {
78*54fd6939SJiyong Park			compatible = "st,stpmic1-regulators";
79*54fd6939SJiyong Park			ldo1-supply = <&v3v3>;
80*54fd6939SJiyong Park			ldo2-supply = <&v3v3>;
81*54fd6939SJiyong Park			ldo3-supply = <&vdd_ddr>;
82*54fd6939SJiyong Park			ldo5-supply = <&v3v3>;
83*54fd6939SJiyong Park			ldo6-supply = <&v3v3>;
84*54fd6939SJiyong Park			pwr_sw1-supply = <&bst_out>;
85*54fd6939SJiyong Park			pwr_sw2-supply = <&bst_out>;
86*54fd6939SJiyong Park
87*54fd6939SJiyong Park			vddcore: buck1 {
88*54fd6939SJiyong Park				regulator-name = "vddcore";
89*54fd6939SJiyong Park				regulator-min-microvolt = <1200000>;
90*54fd6939SJiyong Park				regulator-max-microvolt = <1350000>;
91*54fd6939SJiyong Park				regulator-always-on;
92*54fd6939SJiyong Park				regulator-initial-mode = <0>;
93*54fd6939SJiyong Park				regulator-over-current-protection;
94*54fd6939SJiyong Park			};
95*54fd6939SJiyong Park
96*54fd6939SJiyong Park			vdd_ddr: buck2 {
97*54fd6939SJiyong Park				regulator-name = "vdd_ddr";
98*54fd6939SJiyong Park				regulator-min-microvolt = <1350000>;
99*54fd6939SJiyong Park				regulator-max-microvolt = <1350000>;
100*54fd6939SJiyong Park				regulator-always-on;
101*54fd6939SJiyong Park				regulator-initial-mode = <0>;
102*54fd6939SJiyong Park				regulator-over-current-protection;
103*54fd6939SJiyong Park			};
104*54fd6939SJiyong Park
105*54fd6939SJiyong Park			vdd: buck3 {
106*54fd6939SJiyong Park				regulator-name = "vdd";
107*54fd6939SJiyong Park				regulator-min-microvolt = <3300000>;
108*54fd6939SJiyong Park				regulator-max-microvolt = <3300000>;
109*54fd6939SJiyong Park				regulator-always-on;
110*54fd6939SJiyong Park				st,mask-reset;
111*54fd6939SJiyong Park				regulator-initial-mode = <0>;
112*54fd6939SJiyong Park				regulator-over-current-protection;
113*54fd6939SJiyong Park			};
114*54fd6939SJiyong Park
115*54fd6939SJiyong Park			v3v3: buck4 {
116*54fd6939SJiyong Park				regulator-name = "v3v3";
117*54fd6939SJiyong Park				regulator-min-microvolt = <3300000>;
118*54fd6939SJiyong Park				regulator-max-microvolt = <3300000>;
119*54fd6939SJiyong Park				regulator-always-on;
120*54fd6939SJiyong Park				regulator-over-current-protection;
121*54fd6939SJiyong Park				regulator-initial-mode = <0>;
122*54fd6939SJiyong Park			};
123*54fd6939SJiyong Park
124*54fd6939SJiyong Park			vdda: ldo1 {
125*54fd6939SJiyong Park				regulator-name = "vdda";
126*54fd6939SJiyong Park				regulator-min-microvolt = <2900000>;
127*54fd6939SJiyong Park				regulator-max-microvolt = <2900000>;
128*54fd6939SJiyong Park			};
129*54fd6939SJiyong Park
130*54fd6939SJiyong Park			v2v8: ldo2 {
131*54fd6939SJiyong Park				regulator-name = "v2v8";
132*54fd6939SJiyong Park				regulator-min-microvolt = <2800000>;
133*54fd6939SJiyong Park				regulator-max-microvolt = <2800000>;
134*54fd6939SJiyong Park			};
135*54fd6939SJiyong Park
136*54fd6939SJiyong Park			vtt_ddr: ldo3 {
137*54fd6939SJiyong Park				regulator-name = "vtt_ddr";
138*54fd6939SJiyong Park				regulator-min-microvolt = <500000>;
139*54fd6939SJiyong Park				regulator-max-microvolt = <750000>;
140*54fd6939SJiyong Park				regulator-always-on;
141*54fd6939SJiyong Park				regulator-over-current-protection;
142*54fd6939SJiyong Park			};
143*54fd6939SJiyong Park
144*54fd6939SJiyong Park			vdd_usb: ldo4 {
145*54fd6939SJiyong Park				regulator-name = "vdd_usb";
146*54fd6939SJiyong Park			};
147*54fd6939SJiyong Park
148*54fd6939SJiyong Park			vdd_sd: ldo5 {
149*54fd6939SJiyong Park				regulator-name = "vdd_sd";
150*54fd6939SJiyong Park				regulator-min-microvolt = <2900000>;
151*54fd6939SJiyong Park				regulator-max-microvolt = <2900000>;
152*54fd6939SJiyong Park				regulator-boot-on;
153*54fd6939SJiyong Park			};
154*54fd6939SJiyong Park
155*54fd6939SJiyong Park			v1v8: ldo6 {
156*54fd6939SJiyong Park				regulator-name = "v1v8";
157*54fd6939SJiyong Park				regulator-min-microvolt = <1800000>;
158*54fd6939SJiyong Park				regulator-max-microvolt = <1800000>;
159*54fd6939SJiyong Park			};
160*54fd6939SJiyong Park
161*54fd6939SJiyong Park			vref_ddr: vref_ddr {
162*54fd6939SJiyong Park				regulator-name = "vref_ddr";
163*54fd6939SJiyong Park				regulator-always-on;
164*54fd6939SJiyong Park			};
165*54fd6939SJiyong Park
166*54fd6939SJiyong Park			bst_out: boost {
167*54fd6939SJiyong Park				regulator-name = "bst_out";
168*54fd6939SJiyong Park			};
169*54fd6939SJiyong Park
170*54fd6939SJiyong Park			vbus_otg: pwr_sw1 {
171*54fd6939SJiyong Park				regulator-name = "vbus_otg";
172*54fd6939SJiyong Park			 };
173*54fd6939SJiyong Park
174*54fd6939SJiyong Park			 vbus_sw: pwr_sw2 {
175*54fd6939SJiyong Park				regulator-name = "vbus_sw";
176*54fd6939SJiyong Park				regulator-active-discharge = <1>;
177*54fd6939SJiyong Park			 };
178*54fd6939SJiyong Park		};
179*54fd6939SJiyong Park
180*54fd6939SJiyong Park		onkey {
181*54fd6939SJiyong Park			compatible = "st,stpmic1-onkey";
182*54fd6939SJiyong Park			power-off-time-sec = <10>;
183*54fd6939SJiyong Park			status = "okay";
184*54fd6939SJiyong Park		};
185*54fd6939SJiyong Park
186*54fd6939SJiyong Park		watchdog {
187*54fd6939SJiyong Park			compatible = "st,stpmic1-wdt";
188*54fd6939SJiyong Park			status = "disabled";
189*54fd6939SJiyong Park		};
190*54fd6939SJiyong Park	};
191*54fd6939SJiyong Park};
192*54fd6939SJiyong Park
193*54fd6939SJiyong Park&iwdg2 {
194*54fd6939SJiyong Park	timeout-sec = <32>;
195*54fd6939SJiyong Park	status = "okay";
196*54fd6939SJiyong Park};
197*54fd6939SJiyong Park
198*54fd6939SJiyong Park&pwr_regulators {
199*54fd6939SJiyong Park	vdd-supply = <&vdd>;
200*54fd6939SJiyong Park	vdd_3v3_usbfs-supply = <&vdd_usb>;
201*54fd6939SJiyong Park};
202*54fd6939SJiyong Park
203*54fd6939SJiyong Park&rcc {
204*54fd6939SJiyong Park	secure-status = "disabled";
205*54fd6939SJiyong Park	st,clksrc = <
206*54fd6939SJiyong Park		CLK_MPU_PLL1P
207*54fd6939SJiyong Park		CLK_AXI_PLL2P
208*54fd6939SJiyong Park		CLK_MCU_PLL3P
209*54fd6939SJiyong Park		CLK_PLL12_HSE
210*54fd6939SJiyong Park		CLK_PLL3_HSE
211*54fd6939SJiyong Park		CLK_PLL4_HSE
212*54fd6939SJiyong Park		CLK_RTC_LSE
213*54fd6939SJiyong Park		CLK_MCO1_DISABLED
214*54fd6939SJiyong Park		CLK_MCO2_DISABLED
215*54fd6939SJiyong Park	>;
216*54fd6939SJiyong Park
217*54fd6939SJiyong Park	st,clkdiv = <
218*54fd6939SJiyong Park		1 /*MPU*/
219*54fd6939SJiyong Park		0 /*AXI*/
220*54fd6939SJiyong Park		0 /*MCU*/
221*54fd6939SJiyong Park		1 /*APB1*/
222*54fd6939SJiyong Park		1 /*APB2*/
223*54fd6939SJiyong Park		1 /*APB3*/
224*54fd6939SJiyong Park		1 /*APB4*/
225*54fd6939SJiyong Park		2 /*APB5*/
226*54fd6939SJiyong Park		23 /*RTC*/
227*54fd6939SJiyong Park		0 /*MCO1*/
228*54fd6939SJiyong Park		0 /*MCO2*/
229*54fd6939SJiyong Park	>;
230*54fd6939SJiyong Park
231*54fd6939SJiyong Park	st,pkcs = <
232*54fd6939SJiyong Park		CLK_CKPER_HSE
233*54fd6939SJiyong Park		CLK_FMC_ACLK
234*54fd6939SJiyong Park		CLK_QSPI_ACLK
235*54fd6939SJiyong Park		CLK_ETH_PLL4P
236*54fd6939SJiyong Park		CLK_SDMMC12_PLL4P
237*54fd6939SJiyong Park		CLK_DSI_DSIPLL
238*54fd6939SJiyong Park		CLK_STGEN_HSE
239*54fd6939SJiyong Park		CLK_USBPHY_HSE
240*54fd6939SJiyong Park		CLK_SPI2S1_PLL3Q
241*54fd6939SJiyong Park		CLK_SPI2S23_PLL3Q
242*54fd6939SJiyong Park		CLK_SPI45_HSI
243*54fd6939SJiyong Park		CLK_SPI6_HSI
244*54fd6939SJiyong Park		CLK_I2C46_HSI
245*54fd6939SJiyong Park		CLK_SDMMC3_PLL4P
246*54fd6939SJiyong Park		CLK_USBO_USBPHY
247*54fd6939SJiyong Park		CLK_ADC_CKPER
248*54fd6939SJiyong Park		CLK_CEC_LSE
249*54fd6939SJiyong Park		CLK_I2C12_HSI
250*54fd6939SJiyong Park		CLK_I2C35_HSI
251*54fd6939SJiyong Park		CLK_UART1_HSI
252*54fd6939SJiyong Park		CLK_UART24_HSI
253*54fd6939SJiyong Park		CLK_UART35_HSI
254*54fd6939SJiyong Park		CLK_UART6_HSI
255*54fd6939SJiyong Park		CLK_UART78_HSI
256*54fd6939SJiyong Park		CLK_SPDIF_PLL4P
257*54fd6939SJiyong Park		CLK_FDCAN_PLL4R
258*54fd6939SJiyong Park		CLK_SAI1_PLL3Q
259*54fd6939SJiyong Park		CLK_SAI2_PLL3Q
260*54fd6939SJiyong Park		CLK_SAI3_PLL3Q
261*54fd6939SJiyong Park		CLK_SAI4_PLL3Q
262*54fd6939SJiyong Park		CLK_RNG1_LSI
263*54fd6939SJiyong Park		CLK_RNG2_LSI
264*54fd6939SJiyong Park		CLK_LPTIM1_PCLK1
265*54fd6939SJiyong Park		CLK_LPTIM23_PCLK3
266*54fd6939SJiyong Park		CLK_LPTIM45_LSE
267*54fd6939SJiyong Park	>;
268*54fd6939SJiyong Park
269*54fd6939SJiyong Park	/* VCO = 1300.0 MHz => P = 650 (CPU) */
270*54fd6939SJiyong Park	pll1: st,pll@0 {
271*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
272*54fd6939SJiyong Park		reg = <0>;
273*54fd6939SJiyong Park		cfg = <2 80 0 0 0 PQR(1,0,0)>;
274*54fd6939SJiyong Park		frac = <0x800>;
275*54fd6939SJiyong Park	};
276*54fd6939SJiyong Park
277*54fd6939SJiyong Park	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
278*54fd6939SJiyong Park	pll2: st,pll@1 {
279*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
280*54fd6939SJiyong Park		reg = <1>;
281*54fd6939SJiyong Park		cfg = <2 65 1 0 0 PQR(1,1,1)>;
282*54fd6939SJiyong Park		frac = <0x1400>;
283*54fd6939SJiyong Park	};
284*54fd6939SJiyong Park
285*54fd6939SJiyong Park	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
286*54fd6939SJiyong Park	pll3: st,pll@2 {
287*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
288*54fd6939SJiyong Park		reg = <2>;
289*54fd6939SJiyong Park		cfg = <1 33 1 16 36 PQR(1,1,1)>;
290*54fd6939SJiyong Park		frac = <0x1a04>;
291*54fd6939SJiyong Park	};
292*54fd6939SJiyong Park
293*54fd6939SJiyong Park	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
294*54fd6939SJiyong Park	pll4: st,pll@3 {
295*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
296*54fd6939SJiyong Park		reg = <3>;
297*54fd6939SJiyong Park		cfg = <3 98 5 7 7 PQR(1,1,1)>;
298*54fd6939SJiyong Park	};
299*54fd6939SJiyong Park};
300*54fd6939SJiyong Park
301*54fd6939SJiyong Park&rng1 {
302*54fd6939SJiyong Park	status = "okay";
303*54fd6939SJiyong Park};
304*54fd6939SJiyong Park
305*54fd6939SJiyong Park&rtc {
306*54fd6939SJiyong Park	status = "okay";
307*54fd6939SJiyong Park};
308*54fd6939SJiyong Park
309*54fd6939SJiyong Park&sdmmc1 {
310*54fd6939SJiyong Park	pinctrl-names = "default";
311*54fd6939SJiyong Park	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
312*54fd6939SJiyong Park	disable-wp;
313*54fd6939SJiyong Park	st,sig-dir;
314*54fd6939SJiyong Park	st,neg-edge;
315*54fd6939SJiyong Park	st,use-ckin;
316*54fd6939SJiyong Park	bus-width = <4>;
317*54fd6939SJiyong Park	vmmc-supply = <&vdd_sd>;
318*54fd6939SJiyong Park	sd-uhs-sdr12;
319*54fd6939SJiyong Park	sd-uhs-sdr25;
320*54fd6939SJiyong Park	sd-uhs-sdr50;
321*54fd6939SJiyong Park	sd-uhs-ddr50;
322*54fd6939SJiyong Park	status = "okay";
323*54fd6939SJiyong Park};
324*54fd6939SJiyong Park
325*54fd6939SJiyong Park&sdmmc2 {
326*54fd6939SJiyong Park	pinctrl-names = "default";
327*54fd6939SJiyong Park	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
328*54fd6939SJiyong Park	non-removable;
329*54fd6939SJiyong Park	no-sd;
330*54fd6939SJiyong Park	no-sdio;
331*54fd6939SJiyong Park	st,neg-edge;
332*54fd6939SJiyong Park	bus-width = <8>;
333*54fd6939SJiyong Park	vmmc-supply = <&v3v3>;
334*54fd6939SJiyong Park	vqmmc-supply = <&vdd>;
335*54fd6939SJiyong Park	mmc-ddr-3_3v;
336*54fd6939SJiyong Park	status = "okay";
337*54fd6939SJiyong Park};
338*54fd6939SJiyong Park
339*54fd6939SJiyong Park&uart4 {
340*54fd6939SJiyong Park	pinctrl-names = "default";
341*54fd6939SJiyong Park	pinctrl-0 = <&uart4_pins_a>;
342*54fd6939SJiyong Park	status = "okay";
343*54fd6939SJiyong Park};
344