xref: /aosp_15_r20/external/arm-trusted-firmware/fdts/stm32mp157a-avenger96.dts (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1*54fd6939SJiyong Park// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2*54fd6939SJiyong Park/*
3*54fd6939SJiyong Park * Copyright (C) Arrow Electronics 2019 - All Rights Reserved
4*54fd6939SJiyong Park * Author: Botond Kardos <[email protected]>
5*54fd6939SJiyong Park *
6*54fd6939SJiyong Park * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
7*54fd6939SJiyong Park * Author: Manivannan Sadhasivam <[email protected]>
8*54fd6939SJiyong Park */
9*54fd6939SJiyong Park
10*54fd6939SJiyong Park/dts-v1/;
11*54fd6939SJiyong Park
12*54fd6939SJiyong Park#include "stm32mp157.dtsi"
13*54fd6939SJiyong Park#include "stm32mp15-pinctrl.dtsi"
14*54fd6939SJiyong Park#include "stm32mp15xxac-pinctrl.dtsi"
15*54fd6939SJiyong Park#include <dt-bindings/clock/stm32mp1-clksrc.h>
16*54fd6939SJiyong Park#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
17*54fd6939SJiyong Park
18*54fd6939SJiyong Park/ {
19*54fd6939SJiyong Park	model = "Arrow Electronics STM32MP157A Avenger96 board";
20*54fd6939SJiyong Park	compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
21*54fd6939SJiyong Park
22*54fd6939SJiyong Park	aliases {
23*54fd6939SJiyong Park		mmc0 = &sdmmc1;
24*54fd6939SJiyong Park		serial0 = &uart4;
25*54fd6939SJiyong Park		serial1 = &uart7;
26*54fd6939SJiyong Park	};
27*54fd6939SJiyong Park
28*54fd6939SJiyong Park	chosen {
29*54fd6939SJiyong Park		stdout-path = "serial0:115200n8";
30*54fd6939SJiyong Park	};
31*54fd6939SJiyong Park
32*54fd6939SJiyong Park	memory@c0000000 {
33*54fd6939SJiyong Park		device_type = "memory";
34*54fd6939SJiyong Park		reg = <0xc0000000 0x40000000>;
35*54fd6939SJiyong Park	};
36*54fd6939SJiyong Park};
37*54fd6939SJiyong Park
38*54fd6939SJiyong Park&i2c4 {
39*54fd6939SJiyong Park	pinctrl-names = "default";
40*54fd6939SJiyong Park	pinctrl-0 = <&i2c4_pins_a>;
41*54fd6939SJiyong Park	i2c-scl-rising-time-ns = <185>;
42*54fd6939SJiyong Park	i2c-scl-falling-time-ns = <20>;
43*54fd6939SJiyong Park	status = "okay";
44*54fd6939SJiyong Park
45*54fd6939SJiyong Park	pmic: stpmic@33 {
46*54fd6939SJiyong Park		compatible = "st,stpmic1";
47*54fd6939SJiyong Park		reg = <0x33>;
48*54fd6939SJiyong Park		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
49*54fd6939SJiyong Park		interrupt-controller;
50*54fd6939SJiyong Park		#interrupt-cells = <2>;
51*54fd6939SJiyong Park		status = "okay";
52*54fd6939SJiyong Park
53*54fd6939SJiyong Park		st,main-control-register = <0x04>;
54*54fd6939SJiyong Park		st,vin-control-register = <0xc0>;
55*54fd6939SJiyong Park		st,usb-control-register = <0x30>;
56*54fd6939SJiyong Park
57*54fd6939SJiyong Park		regulators {
58*54fd6939SJiyong Park			compatible = "st,stpmic1-regulators";
59*54fd6939SJiyong Park			ldo1-supply = <&v3v3>;
60*54fd6939SJiyong Park			ldo2-supply = <&v3v3>;
61*54fd6939SJiyong Park			ldo3-supply = <&vdd_ddr>;
62*54fd6939SJiyong Park			ldo5-supply = <&v3v3>;
63*54fd6939SJiyong Park			ldo6-supply = <&v3v3>;
64*54fd6939SJiyong Park			pwr_sw1-supply = <&bst_out>;
65*54fd6939SJiyong Park			pwr_sw2-supply = <&bst_out>;
66*54fd6939SJiyong Park
67*54fd6939SJiyong Park			vddcore: buck1 {
68*54fd6939SJiyong Park				regulator-name = "vddcore";
69*54fd6939SJiyong Park				regulator-min-microvolt = <1200000>;
70*54fd6939SJiyong Park				regulator-max-microvolt = <1350000>;
71*54fd6939SJiyong Park				regulator-always-on;
72*54fd6939SJiyong Park				regulator-initial-mode = <0>;
73*54fd6939SJiyong Park				regulator-over-current-protection;
74*54fd6939SJiyong Park			};
75*54fd6939SJiyong Park
76*54fd6939SJiyong Park			vdd_ddr: buck2 {
77*54fd6939SJiyong Park				regulator-name = "vdd_ddr";
78*54fd6939SJiyong Park				regulator-min-microvolt = <1350000>;
79*54fd6939SJiyong Park				regulator-max-microvolt = <1350000>;
80*54fd6939SJiyong Park				regulator-always-on;
81*54fd6939SJiyong Park				regulator-initial-mode = <0>;
82*54fd6939SJiyong Park				regulator-over-current-protection;
83*54fd6939SJiyong Park			};
84*54fd6939SJiyong Park
85*54fd6939SJiyong Park			vdd: buck3 {
86*54fd6939SJiyong Park				regulator-name = "vdd";
87*54fd6939SJiyong Park				regulator-min-microvolt = <3300000>;
88*54fd6939SJiyong Park				regulator-max-microvolt = <3300000>;
89*54fd6939SJiyong Park				regulator-always-on;
90*54fd6939SJiyong Park				st,mask-reset;
91*54fd6939SJiyong Park				regulator-initial-mode = <0>;
92*54fd6939SJiyong Park				regulator-over-current-protection;
93*54fd6939SJiyong Park			};
94*54fd6939SJiyong Park
95*54fd6939SJiyong Park			v3v3: buck4 {
96*54fd6939SJiyong Park				regulator-name = "v3v3";
97*54fd6939SJiyong Park				regulator-min-microvolt = <3300000>;
98*54fd6939SJiyong Park				regulator-max-microvolt = <3300000>;
99*54fd6939SJiyong Park				regulator-always-on;
100*54fd6939SJiyong Park				regulator-over-current-protection;
101*54fd6939SJiyong Park				regulator-initial-mode = <0>;
102*54fd6939SJiyong Park			};
103*54fd6939SJiyong Park
104*54fd6939SJiyong Park			vdda: ldo1 {
105*54fd6939SJiyong Park				regulator-name = "vdda";
106*54fd6939SJiyong Park				regulator-min-microvolt = <2900000>;
107*54fd6939SJiyong Park				regulator-max-microvolt = <2900000>;
108*54fd6939SJiyong Park			};
109*54fd6939SJiyong Park
110*54fd6939SJiyong Park			v2v8: ldo2 {
111*54fd6939SJiyong Park				regulator-name = "v2v8";
112*54fd6939SJiyong Park				regulator-min-microvolt = <2800000>;
113*54fd6939SJiyong Park				regulator-max-microvolt = <2800000>;
114*54fd6939SJiyong Park			};
115*54fd6939SJiyong Park
116*54fd6939SJiyong Park			vtt_ddr: ldo3 {
117*54fd6939SJiyong Park				regulator-name = "vtt_ddr";
118*54fd6939SJiyong Park				regulator-min-microvolt = <500000>;
119*54fd6939SJiyong Park				regulator-max-microvolt = <750000>;
120*54fd6939SJiyong Park				regulator-always-on;
121*54fd6939SJiyong Park				regulator-over-current-protection;
122*54fd6939SJiyong Park			};
123*54fd6939SJiyong Park
124*54fd6939SJiyong Park			vdd_usb: ldo4 {
125*54fd6939SJiyong Park				regulator-name = "vdd_usb";
126*54fd6939SJiyong Park				regulator-min-microvolt = <3300000>;
127*54fd6939SJiyong Park				regulator-max-microvolt = <3300000>;
128*54fd6939SJiyong Park			};
129*54fd6939SJiyong Park
130*54fd6939SJiyong Park			vdd_sd: ldo5 {
131*54fd6939SJiyong Park				regulator-name = "vdd_sd";
132*54fd6939SJiyong Park				regulator-min-microvolt = <2900000>;
133*54fd6939SJiyong Park				regulator-max-microvolt = <2900000>;
134*54fd6939SJiyong Park				regulator-boot-on;
135*54fd6939SJiyong Park			};
136*54fd6939SJiyong Park
137*54fd6939SJiyong Park			v1v8: ldo6 {
138*54fd6939SJiyong Park				regulator-name = "v1v8";
139*54fd6939SJiyong Park				regulator-min-microvolt = <1800000>;
140*54fd6939SJiyong Park				regulator-max-microvolt = <1800000>;
141*54fd6939SJiyong Park			};
142*54fd6939SJiyong Park
143*54fd6939SJiyong Park			vref_ddr: vref_ddr {
144*54fd6939SJiyong Park				regulator-name = "vref_ddr";
145*54fd6939SJiyong Park				regulator-always-on;
146*54fd6939SJiyong Park				regulator-over-current-protection;
147*54fd6939SJiyong Park			};
148*54fd6939SJiyong Park
149*54fd6939SJiyong Park			bst_out: boost {
150*54fd6939SJiyong Park				regulator-name = "bst_out";
151*54fd6939SJiyong Park			};
152*54fd6939SJiyong Park
153*54fd6939SJiyong Park			vbus_otg: pwr_sw1 {
154*54fd6939SJiyong Park				regulator-name = "vbus_otg";
155*54fd6939SJiyong Park			};
156*54fd6939SJiyong Park
157*54fd6939SJiyong Park			vbus_sw: pwr_sw2 {
158*54fd6939SJiyong Park				regulator-name = "vbus_sw";
159*54fd6939SJiyong Park				regulator-active-discharge = <1>;
160*54fd6939SJiyong Park			};
161*54fd6939SJiyong Park		};
162*54fd6939SJiyong Park	};
163*54fd6939SJiyong Park};
164*54fd6939SJiyong Park
165*54fd6939SJiyong Park&iwdg2 {
166*54fd6939SJiyong Park	timeout-sec = <32>;
167*54fd6939SJiyong Park	status = "okay";
168*54fd6939SJiyong Park	secure-status = "okay";
169*54fd6939SJiyong Park};
170*54fd6939SJiyong Park
171*54fd6939SJiyong Park&pwr_regulators {
172*54fd6939SJiyong Park	vdd-supply = <&vdd>;
173*54fd6939SJiyong Park	vdd_3v3_usbfs-supply = <&vdd_usb>;
174*54fd6939SJiyong Park};
175*54fd6939SJiyong Park
176*54fd6939SJiyong Park&rcc {
177*54fd6939SJiyong Park	secure-status = "disabled";
178*54fd6939SJiyong Park	st,clksrc = <
179*54fd6939SJiyong Park		CLK_MPU_PLL1P
180*54fd6939SJiyong Park		CLK_AXI_PLL2P
181*54fd6939SJiyong Park		CLK_MCU_PLL3P
182*54fd6939SJiyong Park		CLK_PLL12_HSE
183*54fd6939SJiyong Park		CLK_PLL3_HSE
184*54fd6939SJiyong Park		CLK_PLL4_HSE
185*54fd6939SJiyong Park		CLK_RTC_LSE
186*54fd6939SJiyong Park		CLK_MCO1_DISABLED
187*54fd6939SJiyong Park		CLK_MCO2_DISABLED
188*54fd6939SJiyong Park	>;
189*54fd6939SJiyong Park
190*54fd6939SJiyong Park	st,clkdiv = <
191*54fd6939SJiyong Park		1 /*MPU*/
192*54fd6939SJiyong Park		0 /*AXI*/
193*54fd6939SJiyong Park		0 /*MCU*/
194*54fd6939SJiyong Park		1 /*APB1*/
195*54fd6939SJiyong Park		1 /*APB2*/
196*54fd6939SJiyong Park		1 /*APB3*/
197*54fd6939SJiyong Park		1 /*APB4*/
198*54fd6939SJiyong Park		2 /*APB5*/
199*54fd6939SJiyong Park		23 /*RTC*/
200*54fd6939SJiyong Park		0 /*MCO1*/
201*54fd6939SJiyong Park		0 /*MCO2*/
202*54fd6939SJiyong Park	>;
203*54fd6939SJiyong Park
204*54fd6939SJiyong Park	st,pkcs = <
205*54fd6939SJiyong Park		CLK_CKPER_HSE
206*54fd6939SJiyong Park		CLK_FMC_ACLK
207*54fd6939SJiyong Park		CLK_QSPI_ACLK
208*54fd6939SJiyong Park		CLK_ETH_DISABLED
209*54fd6939SJiyong Park		CLK_SDMMC12_PLL4P
210*54fd6939SJiyong Park		CLK_DSI_DSIPLL
211*54fd6939SJiyong Park		CLK_STGEN_HSE
212*54fd6939SJiyong Park		CLK_USBPHY_HSE
213*54fd6939SJiyong Park		CLK_SPI2S1_PLL3Q
214*54fd6939SJiyong Park		CLK_SPI2S23_PLL3Q
215*54fd6939SJiyong Park		CLK_SPI45_HSI
216*54fd6939SJiyong Park		CLK_SPI6_HSI
217*54fd6939SJiyong Park		CLK_I2C46_HSI
218*54fd6939SJiyong Park		CLK_SDMMC3_PLL4P
219*54fd6939SJiyong Park		CLK_USBO_USBPHY
220*54fd6939SJiyong Park		CLK_ADC_CKPER
221*54fd6939SJiyong Park		CLK_CEC_LSE
222*54fd6939SJiyong Park		CLK_I2C12_HSI
223*54fd6939SJiyong Park		CLK_I2C35_HSI
224*54fd6939SJiyong Park		CLK_UART1_HSI
225*54fd6939SJiyong Park		CLK_UART24_HSI
226*54fd6939SJiyong Park		CLK_UART35_HSI
227*54fd6939SJiyong Park		CLK_UART6_HSI
228*54fd6939SJiyong Park		CLK_UART78_HSI
229*54fd6939SJiyong Park		CLK_SPDIF_PLL4P
230*54fd6939SJiyong Park		CLK_FDCAN_PLL4R
231*54fd6939SJiyong Park		CLK_SAI1_PLL3Q
232*54fd6939SJiyong Park		CLK_SAI2_PLL3Q
233*54fd6939SJiyong Park		CLK_SAI3_PLL3Q
234*54fd6939SJiyong Park		CLK_SAI4_PLL3Q
235*54fd6939SJiyong Park		CLK_RNG1_LSI
236*54fd6939SJiyong Park		CLK_RNG2_LSI
237*54fd6939SJiyong Park		CLK_LPTIM1_PCLK1
238*54fd6939SJiyong Park		CLK_LPTIM23_PCLK3
239*54fd6939SJiyong Park		CLK_LPTIM45_LSE
240*54fd6939SJiyong Park	>;
241*54fd6939SJiyong Park
242*54fd6939SJiyong Park	/* VCO = 1300.0 MHz => P = 650 (CPU) */
243*54fd6939SJiyong Park	pll1: st,pll@0 {
244*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
245*54fd6939SJiyong Park		reg = <0>;
246*54fd6939SJiyong Park		cfg = <2 80 0 0 0 PQR(1,0,0)>;
247*54fd6939SJiyong Park		frac = <0x800>;
248*54fd6939SJiyong Park	};
249*54fd6939SJiyong Park
250*54fd6939SJiyong Park	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
251*54fd6939SJiyong Park	pll2: st,pll@1 {
252*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
253*54fd6939SJiyong Park		reg = <1>;
254*54fd6939SJiyong Park		cfg = <2 65 1 0 0 PQR(1,1,1)>;
255*54fd6939SJiyong Park		frac = <0x1400>;
256*54fd6939SJiyong Park	};
257*54fd6939SJiyong Park
258*54fd6939SJiyong Park	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
259*54fd6939SJiyong Park	pll3: st,pll@2 {
260*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
261*54fd6939SJiyong Park		reg = <2>;
262*54fd6939SJiyong Park		cfg = <1 33 1 16 36 PQR(1,1,1)>;
263*54fd6939SJiyong Park		frac = <0x1a04>;
264*54fd6939SJiyong Park	};
265*54fd6939SJiyong Park
266*54fd6939SJiyong Park	/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
267*54fd6939SJiyong Park	pll4: st,pll@3 {
268*54fd6939SJiyong Park		compatible = "st,stm32mp1-pll";
269*54fd6939SJiyong Park		reg = <3>;
270*54fd6939SJiyong Park		cfg = <1 39 3 11 4 PQR(1,1,1)>;
271*54fd6939SJiyong Park	};
272*54fd6939SJiyong Park};
273*54fd6939SJiyong Park
274*54fd6939SJiyong Park&rng1 {
275*54fd6939SJiyong Park	status = "okay";
276*54fd6939SJiyong Park};
277*54fd6939SJiyong Park
278*54fd6939SJiyong Park&rtc {
279*54fd6939SJiyong Park	status = "okay";
280*54fd6939SJiyong Park};
281*54fd6939SJiyong Park
282*54fd6939SJiyong Park&sdmmc1 {
283*54fd6939SJiyong Park	pinctrl-names = "default";
284*54fd6939SJiyong Park	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
285*54fd6939SJiyong Park	st,sig-dir;
286*54fd6939SJiyong Park	st,neg-edge;
287*54fd6939SJiyong Park	st,use-ckin;
288*54fd6939SJiyong Park	bus-width = <4>;
289*54fd6939SJiyong Park	vmmc-supply = <&vdd_sd>;
290*54fd6939SJiyong Park	status = "okay";
291*54fd6939SJiyong Park};
292*54fd6939SJiyong Park
293*54fd6939SJiyong Park&uart4 {
294*54fd6939SJiyong Park	/* On Low speed expansion header */
295*54fd6939SJiyong Park	label = "LS-UART1";
296*54fd6939SJiyong Park	pinctrl-names = "default";
297*54fd6939SJiyong Park	pinctrl-0 = <&uart4_pins_b>;
298*54fd6939SJiyong Park	status = "okay";
299*54fd6939SJiyong Park};
300*54fd6939SJiyong Park
301*54fd6939SJiyong Park&uart7 {
302*54fd6939SJiyong Park	/* On Low speed expansion header */
303*54fd6939SJiyong Park	label = "LS-UART0";
304*54fd6939SJiyong Park	pinctrl-names = "default";
305*54fd6939SJiyong Park	pinctrl-0 = <&uart7_pins_a>;
306*54fd6939SJiyong Park	status = "okay";
307*54fd6939SJiyong Park};
308