1*54fd6939SJiyong Park// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2*54fd6939SJiyong Park/* 3*54fd6939SJiyong Park * Copyright (c) 2021, STMicroelectronics - All Rights Reserved 4*54fd6939SJiyong Park */ 5*54fd6939SJiyong Park 6*54fd6939SJiyong Park#include <common/tbbr/tbbr_img_def.h> 7*54fd6939SJiyong Park#include <dt-bindings/soc/stm32mp15-tzc400.h> 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park#include <platform_def.h> 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park#ifndef DDR_SIZE 12*54fd6939SJiyong Park#error "DDR_SIZE is not defined" 13*54fd6939SJiyong Park#endif 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park#define DDR_NS_BASE STM32MP_DDR_BASE 16*54fd6939SJiyong Park#ifdef AARCH32_SP_OPTEE 17*54fd6939SJiyong Park/* OP-TEE reserved shared memory: located at DDR top */ 18*54fd6939SJiyong Park#define DDR_SHARE_SIZE STM32MP_DDR_SHMEM_SIZE 19*54fd6939SJiyong Park#define DDR_SHARE_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SHARE_SIZE)) 20*54fd6939SJiyong Park/* OP-TEE secure memory: located right below OP-TEE reserved shared memory */ 21*54fd6939SJiyong Park#define DDR_SEC_SIZE STM32MP_DDR_S_SIZE 22*54fd6939SJiyong Park#define DDR_SEC_BASE (DDR_SHARE_BASE - DDR_SEC_SIZE) 23*54fd6939SJiyong Park#define DDR_NS_SIZE (DDR_SEC_BASE - DDR_NS_BASE) 24*54fd6939SJiyong Park#else /* !AARCH32_SP_OPTEE */ 25*54fd6939SJiyong Park#define DDR_NS_SIZE DDR_SIZE 26*54fd6939SJiyong Park#endif /* AARCH32_SP_OPTEE */ 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park/dts-v1/; 29*54fd6939SJiyong Park 30*54fd6939SJiyong Park/ { 31*54fd6939SJiyong Park dtb-registry { 32*54fd6939SJiyong Park compatible = "fconf,dyn_cfg-dtb_registry"; 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park hw-config { 35*54fd6939SJiyong Park load-address = <0x0 STM32MP_HW_CONFIG_BASE>; 36*54fd6939SJiyong Park max-size = <STM32MP_HW_CONFIG_MAX_SIZE>; 37*54fd6939SJiyong Park id = <HW_CONFIG_ID>; 38*54fd6939SJiyong Park }; 39*54fd6939SJiyong Park 40*54fd6939SJiyong Park nt_fw { 41*54fd6939SJiyong Park load-address = <0x0 STM32MP_BL33_BASE>; 42*54fd6939SJiyong Park max-size = <STM32MP_BL33_MAX_SIZE>; 43*54fd6939SJiyong Park id = <BL33_IMAGE_ID>; 44*54fd6939SJiyong Park }; 45*54fd6939SJiyong Park 46*54fd6939SJiyong Park#ifdef AARCH32_SP_OPTEE 47*54fd6939SJiyong Park tos_fw { 48*54fd6939SJiyong Park load-address = <0x0 STM32MP_OPTEE_BASE>; 49*54fd6939SJiyong Park max-size = <STM32MP_OPTEE_SIZE>; 50*54fd6939SJiyong Park id = <BL32_IMAGE_ID>; 51*54fd6939SJiyong Park }; 52*54fd6939SJiyong Park#else 53*54fd6939SJiyong Park tos_fw { 54*54fd6939SJiyong Park load-address = <0x0 STM32MP_BL32_BASE>; 55*54fd6939SJiyong Park max-size = <STM32MP_BL32_SIZE>; 56*54fd6939SJiyong Park id = <BL32_IMAGE_ID>; 57*54fd6939SJiyong Park }; 58*54fd6939SJiyong Park 59*54fd6939SJiyong Park tos_fw-config { 60*54fd6939SJiyong Park load-address = <0x0 STM32MP_BL32_DTB_BASE>; 61*54fd6939SJiyong Park max-size = <STM32MP_BL32_DTB_SIZE>; 62*54fd6939SJiyong Park id = <TOS_FW_CONFIG_ID>; 63*54fd6939SJiyong Park }; 64*54fd6939SJiyong Park#endif 65*54fd6939SJiyong Park }; 66*54fd6939SJiyong Park 67*54fd6939SJiyong Park st-mem-firewall { 68*54fd6939SJiyong Park compatible = "st,mem-firewall"; 69*54fd6939SJiyong Park#ifdef AARCH32_SP_OPTEE 70*54fd6939SJiyong Park memory-ranges = < 71*54fd6939SJiyong Park DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR 72*54fd6939SJiyong Park DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0 73*54fd6939SJiyong Park DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE 74*54fd6939SJiyong Park TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID)>; 75*54fd6939SJiyong Park#else 76*54fd6939SJiyong Park memory-ranges = < 77*54fd6939SJiyong Park DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR>; 78*54fd6939SJiyong Park#endif 79*54fd6939SJiyong Park }; 80*54fd6939SJiyong Park}; 81