1*54fd6939SJiyong Park// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2*54fd6939SJiyong Park/* 3*54fd6939SJiyong Park * Copyright (c) 2018-2021, STMicroelectronics - All Rights Reserved 4*54fd6939SJiyong Park */ 5*54fd6939SJiyong Park 6*54fd6939SJiyong Park/* 7*54fd6939SJiyong Park * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs 8*54fd6939SJiyong Park * DDR type: DDR3 / DDR3L 9*54fd6939SJiyong Park * DDR width: 16bits 10*54fd6939SJiyong Park * DDR density: 4Gb 11*54fd6939SJiyong Park * System frequency: 533000Khz 12*54fd6939SJiyong Park * Relaxed Timing Mode: false 13*54fd6939SJiyong Park * Address mapping type: RBC 14*54fd6939SJiyong Park * 15*54fd6939SJiyong Park * Save Date: 2020.02.20, save Time: 18:45:20 16*54fd6939SJiyong Park */ 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" 19*54fd6939SJiyong Park#define DDR_MEM_SPEED 533000 20*54fd6939SJiyong Park#define DDR_MEM_SIZE 0x20000000 21*54fd6939SJiyong Park 22*54fd6939SJiyong Park#define DDR_MSTR 0x00041401 23*54fd6939SJiyong Park#define DDR_MRCTRL0 0x00000010 24*54fd6939SJiyong Park#define DDR_MRCTRL1 0x00000000 25*54fd6939SJiyong Park#define DDR_DERATEEN 0x00000000 26*54fd6939SJiyong Park#define DDR_DERATEINT 0x00800000 27*54fd6939SJiyong Park#define DDR_PWRCTL 0x00000000 28*54fd6939SJiyong Park#define DDR_PWRTMG 0x00400010 29*54fd6939SJiyong Park#define DDR_HWLPCTL 0x00000000 30*54fd6939SJiyong Park#define DDR_RFSHCTL0 0x00210000 31*54fd6939SJiyong Park#define DDR_RFSHCTL3 0x00000000 32*54fd6939SJiyong Park#define DDR_RFSHTMG 0x0081008B 33*54fd6939SJiyong Park#define DDR_CRCPARCTL0 0x00000000 34*54fd6939SJiyong Park#define DDR_DRAMTMG0 0x121B2414 35*54fd6939SJiyong Park#define DDR_DRAMTMG1 0x000A041C 36*54fd6939SJiyong Park#define DDR_DRAMTMG2 0x0608090F 37*54fd6939SJiyong Park#define DDR_DRAMTMG3 0x0050400C 38*54fd6939SJiyong Park#define DDR_DRAMTMG4 0x08040608 39*54fd6939SJiyong Park#define DDR_DRAMTMG5 0x06060403 40*54fd6939SJiyong Park#define DDR_DRAMTMG6 0x02020002 41*54fd6939SJiyong Park#define DDR_DRAMTMG7 0x00000202 42*54fd6939SJiyong Park#define DDR_DRAMTMG8 0x00001005 43*54fd6939SJiyong Park#define DDR_DRAMTMG14 0x000000A0 44*54fd6939SJiyong Park#define DDR_ZQCTL0 0xC2000040 45*54fd6939SJiyong Park#define DDR_DFITMG0 0x02060105 46*54fd6939SJiyong Park#define DDR_DFITMG1 0x00000202 47*54fd6939SJiyong Park#define DDR_DFILPCFG0 0x07000000 48*54fd6939SJiyong Park#define DDR_DFIUPD0 0xC0400003 49*54fd6939SJiyong Park#define DDR_DFIUPD1 0x00000000 50*54fd6939SJiyong Park#define DDR_DFIUPD2 0x00000000 51*54fd6939SJiyong Park#define DDR_DFIPHYMSTR 0x00000000 52*54fd6939SJiyong Park#define DDR_ODTCFG 0x06000600 53*54fd6939SJiyong Park#define DDR_ODTMAP 0x00000001 54*54fd6939SJiyong Park#define DDR_SCHED 0x00000C01 55*54fd6939SJiyong Park#define DDR_SCHED1 0x00000000 56*54fd6939SJiyong Park#define DDR_PERFHPR1 0x01000001 57*54fd6939SJiyong Park#define DDR_PERFLPR1 0x08000200 58*54fd6939SJiyong Park#define DDR_PERFWR1 0x08000400 59*54fd6939SJiyong Park#define DDR_DBG0 0x00000000 60*54fd6939SJiyong Park#define DDR_DBG1 0x00000000 61*54fd6939SJiyong Park#define DDR_DBGCMD 0x00000000 62*54fd6939SJiyong Park#define DDR_POISONCFG 0x00000000 63*54fd6939SJiyong Park#define DDR_PCCFG 0x00000010 64*54fd6939SJiyong Park#define DDR_PCFGR_0 0x00010000 65*54fd6939SJiyong Park#define DDR_PCFGW_0 0x00000000 66*54fd6939SJiyong Park#define DDR_PCFGQOS0_0 0x02100C03 67*54fd6939SJiyong Park#define DDR_PCFGQOS1_0 0x00800100 68*54fd6939SJiyong Park#define DDR_PCFGWQOS0_0 0x01100C03 69*54fd6939SJiyong Park#define DDR_PCFGWQOS1_0 0x01000200 70*54fd6939SJiyong Park#define DDR_PCFGR_1 0x00010000 71*54fd6939SJiyong Park#define DDR_PCFGW_1 0x00000000 72*54fd6939SJiyong Park#define DDR_PCFGQOS0_1 0x02100C03 73*54fd6939SJiyong Park#define DDR_PCFGQOS1_1 0x00800040 74*54fd6939SJiyong Park#define DDR_PCFGWQOS0_1 0x01100C03 75*54fd6939SJiyong Park#define DDR_PCFGWQOS1_1 0x01000200 76*54fd6939SJiyong Park#define DDR_ADDRMAP1 0x00070707 77*54fd6939SJiyong Park#define DDR_ADDRMAP2 0x00000000 78*54fd6939SJiyong Park#define DDR_ADDRMAP3 0x1F000000 79*54fd6939SJiyong Park#define DDR_ADDRMAP4 0x00001F1F 80*54fd6939SJiyong Park#define DDR_ADDRMAP5 0x06060606 81*54fd6939SJiyong Park#define DDR_ADDRMAP6 0x0F060606 82*54fd6939SJiyong Park#define DDR_ADDRMAP9 0x00000000 83*54fd6939SJiyong Park#define DDR_ADDRMAP10 0x00000000 84*54fd6939SJiyong Park#define DDR_ADDRMAP11 0x00000000 85*54fd6939SJiyong Park#define DDR_PGCR 0x01442E02 86*54fd6939SJiyong Park#define DDR_PTR0 0x0022AA5B 87*54fd6939SJiyong Park#define DDR_PTR1 0x04841104 88*54fd6939SJiyong Park#define DDR_PTR2 0x042DA068 89*54fd6939SJiyong Park#define DDR_ACIOCR 0x10400812 90*54fd6939SJiyong Park#define DDR_DXCCR 0x00000C40 91*54fd6939SJiyong Park#define DDR_DSGCR 0xF200011F 92*54fd6939SJiyong Park#define DDR_DCR 0x0000000B 93*54fd6939SJiyong Park#define DDR_DTPR0 0x38D488D0 94*54fd6939SJiyong Park#define DDR_DTPR1 0x098B00D8 95*54fd6939SJiyong Park#define DDR_DTPR2 0x10023600 96*54fd6939SJiyong Park#define DDR_MR0 0x00000840 97*54fd6939SJiyong Park#define DDR_MR1 0x00000000 98*54fd6939SJiyong Park#define DDR_MR2 0x00000208 99*54fd6939SJiyong Park#define DDR_MR3 0x00000000 100*54fd6939SJiyong Park#define DDR_ODTCR 0x00010000 101*54fd6939SJiyong Park#define DDR_ZQ0CR1 0x00000038 102*54fd6939SJiyong Park#define DDR_DX0GCR 0x0000CE81 103*54fd6939SJiyong Park#define DDR_DX0DLLCR 0x40000000 104*54fd6939SJiyong Park#define DDR_DX0DQTR 0xFFFFFFFF 105*54fd6939SJiyong Park#define DDR_DX0DQSTR 0x3DB02000 106*54fd6939SJiyong Park#define DDR_DX1GCR 0x0000CE81 107*54fd6939SJiyong Park#define DDR_DX1DLLCR 0x40000000 108*54fd6939SJiyong Park#define DDR_DX1DQTR 0xFFFFFFFF 109*54fd6939SJiyong Park#define DDR_DX1DQSTR 0x3DB02000 110*54fd6939SJiyong Park#define DDR_DX2GCR 0x0000CE80 111*54fd6939SJiyong Park#define DDR_DX2DLLCR 0x40000000 112*54fd6939SJiyong Park#define DDR_DX2DQTR 0xFFFFFFFF 113*54fd6939SJiyong Park#define DDR_DX2DQSTR 0x3DB02000 114*54fd6939SJiyong Park#define DDR_DX3GCR 0x0000CE80 115*54fd6939SJiyong Park#define DDR_DX3DLLCR 0x40000000 116*54fd6939SJiyong Park#define DDR_DX3DQTR 0xFFFFFFFF 117*54fd6939SJiyong Park#define DDR_DX3DQSTR 0x3DB02000 118*54fd6939SJiyong Park 119*54fd6939SJiyong Park#include "stm32mp15-ddr.dtsi" 120