xref: /aosp_15_r20/external/arm-trusted-firmware/fdts/rtsm_ve-motherboard-aarch32.dtsi (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1*54fd6939SJiyong Park/*
2*54fd6939SJiyong Park * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park	motherboard {
8*54fd6939SJiyong Park		arm,v2m-memory-map = "rs1";
9*54fd6939SJiyong Park		compatible = "arm,vexpress,v2m-p1", "simple-bus";
10*54fd6939SJiyong Park		#address-cells = <2>; /* SMB chipselect number and offset */
11*54fd6939SJiyong Park		#size-cells = <1>;
12*54fd6939SJiyong Park		#interrupt-cells = <1>;
13*54fd6939SJiyong Park		ranges;
14*54fd6939SJiyong Park
15*54fd6939SJiyong Park		flash@0,00000000 {
16*54fd6939SJiyong Park			compatible = "arm,vexpress-flash", "cfi-flash";
17*54fd6939SJiyong Park			reg = <0 0x00000000 0x04000000>,
18*54fd6939SJiyong Park			      <4 0x00000000 0x04000000>;
19*54fd6939SJiyong Park			bank-width = <4>;
20*54fd6939SJiyong Park		};
21*54fd6939SJiyong Park
22*54fd6939SJiyong Park		vram@2,00000000 {
23*54fd6939SJiyong Park			compatible = "arm,vexpress-vram";
24*54fd6939SJiyong Park			reg = <2 0x00000000 0x00800000>;
25*54fd6939SJiyong Park		};
26*54fd6939SJiyong Park
27*54fd6939SJiyong Park		ethernet@2,02000000 {
28*54fd6939SJiyong Park			compatible = "smsc,lan91c111";
29*54fd6939SJiyong Park			reg = <2 0x02000000 0x10000>;
30*54fd6939SJiyong Park			interrupts = <15>;
31*54fd6939SJiyong Park		};
32*54fd6939SJiyong Park
33*54fd6939SJiyong Park		v2m_clk24mhz: clk24mhz {
34*54fd6939SJiyong Park			compatible = "fixed-clock";
35*54fd6939SJiyong Park			#clock-cells = <0>;
36*54fd6939SJiyong Park			clock-frequency = <24000000>;
37*54fd6939SJiyong Park			clock-output-names = "v2m:clk24mhz";
38*54fd6939SJiyong Park		};
39*54fd6939SJiyong Park
40*54fd6939SJiyong Park		v2m_refclk1mhz: refclk1mhz {
41*54fd6939SJiyong Park			compatible = "fixed-clock";
42*54fd6939SJiyong Park			#clock-cells = <0>;
43*54fd6939SJiyong Park			clock-frequency = <1000000>;
44*54fd6939SJiyong Park			clock-output-names = "v2m:refclk1mhz";
45*54fd6939SJiyong Park		};
46*54fd6939SJiyong Park
47*54fd6939SJiyong Park		v2m_refclk32khz: refclk32khz {
48*54fd6939SJiyong Park			compatible = "fixed-clock";
49*54fd6939SJiyong Park			#clock-cells = <0>;
50*54fd6939SJiyong Park			clock-frequency = <32768>;
51*54fd6939SJiyong Park			clock-output-names = "v2m:refclk32khz";
52*54fd6939SJiyong Park		};
53*54fd6939SJiyong Park
54*54fd6939SJiyong Park		iofpga@3,00000000 {
55*54fd6939SJiyong Park			compatible = "arm,amba-bus", "simple-bus";
56*54fd6939SJiyong Park			#address-cells = <1>;
57*54fd6939SJiyong Park			#size-cells = <1>;
58*54fd6939SJiyong Park			ranges = <0 3 0 0x200000>;
59*54fd6939SJiyong Park
60*54fd6939SJiyong Park			v2m_sysreg: sysreg@10000 {
61*54fd6939SJiyong Park				compatible = "arm,vexpress-sysreg";
62*54fd6939SJiyong Park				reg = <0x010000 0x1000>;
63*54fd6939SJiyong Park				gpio-controller;
64*54fd6939SJiyong Park				#gpio-cells = <2>;
65*54fd6939SJiyong Park			};
66*54fd6939SJiyong Park
67*54fd6939SJiyong Park			v2m_sysctl: sysctl@20000 {
68*54fd6939SJiyong Park				compatible = "arm,sp810", "arm,primecell";
69*54fd6939SJiyong Park				reg = <0x020000 0x1000>;
70*54fd6939SJiyong Park				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
71*54fd6939SJiyong Park				clock-names = "refclk", "timclk", "apb_pclk";
72*54fd6939SJiyong Park				#clock-cells = <1>;
73*54fd6939SJiyong Park				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
74*54fd6939SJiyong Park			};
75*54fd6939SJiyong Park
76*54fd6939SJiyong Park			aaci@40000 {
77*54fd6939SJiyong Park				compatible = "arm,pl041", "arm,primecell";
78*54fd6939SJiyong Park				reg = <0x040000 0x1000>;
79*54fd6939SJiyong Park				interrupts = <11>;
80*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>;
81*54fd6939SJiyong Park				clock-names = "apb_pclk";
82*54fd6939SJiyong Park			};
83*54fd6939SJiyong Park
84*54fd6939SJiyong Park			mmci@50000 {
85*54fd6939SJiyong Park				compatible = "arm,pl180", "arm,primecell";
86*54fd6939SJiyong Park				reg = <0x050000 0x1000>;
87*54fd6939SJiyong Park				interrupts = <9 10>;
88*54fd6939SJiyong Park				cd-gpios = <&v2m_sysreg 0 0>;
89*54fd6939SJiyong Park				wp-gpios = <&v2m_sysreg 1 0>;
90*54fd6939SJiyong Park				max-frequency = <12000000>;
91*54fd6939SJiyong Park				vmmc-supply = <&v2m_fixed_3v3>;
92*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
93*54fd6939SJiyong Park				clock-names = "mclk", "apb_pclk";
94*54fd6939SJiyong Park			};
95*54fd6939SJiyong Park
96*54fd6939SJiyong Park			kmi@60000 {
97*54fd6939SJiyong Park				compatible = "arm,pl050", "arm,primecell";
98*54fd6939SJiyong Park				reg = <0x060000 0x1000>;
99*54fd6939SJiyong Park				interrupts = <12>;
100*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
101*54fd6939SJiyong Park				clock-names = "KMIREFCLK", "apb_pclk";
102*54fd6939SJiyong Park			};
103*54fd6939SJiyong Park
104*54fd6939SJiyong Park			kmi@70000 {
105*54fd6939SJiyong Park				compatible = "arm,pl050", "arm,primecell";
106*54fd6939SJiyong Park				reg = <0x070000 0x1000>;
107*54fd6939SJiyong Park				interrupts = <13>;
108*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
109*54fd6939SJiyong Park				clock-names = "KMIREFCLK", "apb_pclk";
110*54fd6939SJiyong Park			};
111*54fd6939SJiyong Park
112*54fd6939SJiyong Park			v2m_serial0: uart@90000 {
113*54fd6939SJiyong Park				compatible = "arm,pl011", "arm,primecell";
114*54fd6939SJiyong Park				reg = <0x090000 0x1000>;
115*54fd6939SJiyong Park				interrupts = <5>;
116*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
117*54fd6939SJiyong Park				clock-names = "uartclk", "apb_pclk";
118*54fd6939SJiyong Park			};
119*54fd6939SJiyong Park
120*54fd6939SJiyong Park			v2m_serial1: uart@a0000 {
121*54fd6939SJiyong Park				compatible = "arm,pl011", "arm,primecell";
122*54fd6939SJiyong Park				reg = <0x0a0000 0x1000>;
123*54fd6939SJiyong Park				interrupts = <6>;
124*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
125*54fd6939SJiyong Park				clock-names = "uartclk", "apb_pclk";
126*54fd6939SJiyong Park			};
127*54fd6939SJiyong Park
128*54fd6939SJiyong Park			v2m_serial2: uart@b0000 {
129*54fd6939SJiyong Park				compatible = "arm,pl011", "arm,primecell";
130*54fd6939SJiyong Park				reg = <0x0b0000 0x1000>;
131*54fd6939SJiyong Park				interrupts = <7>;
132*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
133*54fd6939SJiyong Park				clock-names = "uartclk", "apb_pclk";
134*54fd6939SJiyong Park			};
135*54fd6939SJiyong Park
136*54fd6939SJiyong Park			v2m_serial3: uart@c0000 {
137*54fd6939SJiyong Park				compatible = "arm,pl011", "arm,primecell";
138*54fd6939SJiyong Park				reg = <0x0c0000 0x1000>;
139*54fd6939SJiyong Park				interrupts = <8>;
140*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
141*54fd6939SJiyong Park				clock-names = "uartclk", "apb_pclk";
142*54fd6939SJiyong Park			};
143*54fd6939SJiyong Park
144*54fd6939SJiyong Park			wdt@f0000 {
145*54fd6939SJiyong Park				compatible = "arm,sp805", "arm,primecell";
146*54fd6939SJiyong Park				reg = <0x0f0000 0x1000>;
147*54fd6939SJiyong Park				interrupts = <0>;
148*54fd6939SJiyong Park				clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
149*54fd6939SJiyong Park				clock-names = "wdogclk", "apb_pclk";
150*54fd6939SJiyong Park			};
151*54fd6939SJiyong Park
152*54fd6939SJiyong Park			v2m_timer01: timer@110000 {
153*54fd6939SJiyong Park				compatible = "arm,sp804", "arm,primecell";
154*54fd6939SJiyong Park				reg = <0x110000 0x1000>;
155*54fd6939SJiyong Park				interrupts = <2>;
156*54fd6939SJiyong Park				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
157*54fd6939SJiyong Park				clock-names = "timclken1", "timclken2", "apb_pclk";
158*54fd6939SJiyong Park			};
159*54fd6939SJiyong Park
160*54fd6939SJiyong Park			v2m_timer23: timer@120000 {
161*54fd6939SJiyong Park				compatible = "arm,sp804", "arm,primecell";
162*54fd6939SJiyong Park				reg = <0x120000 0x1000>;
163*54fd6939SJiyong Park				interrupts = <3>;
164*54fd6939SJiyong Park				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
165*54fd6939SJiyong Park				clock-names = "timclken1", "timclken2", "apb_pclk";
166*54fd6939SJiyong Park			};
167*54fd6939SJiyong Park
168*54fd6939SJiyong Park			rtc@170000 {
169*54fd6939SJiyong Park				compatible = "arm,pl031", "arm,primecell";
170*54fd6939SJiyong Park				reg = <0x170000 0x1000>;
171*54fd6939SJiyong Park				interrupts = <4>;
172*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>;
173*54fd6939SJiyong Park				clock-names = "apb_pclk";
174*54fd6939SJiyong Park			};
175*54fd6939SJiyong Park
176*54fd6939SJiyong Park			clcd@1f0000 {
177*54fd6939SJiyong Park				compatible = "arm,pl111", "arm,primecell";
178*54fd6939SJiyong Park				reg = <0x1f0000 0x1000>;
179*54fd6939SJiyong Park				interrupts = <14>;
180*54fd6939SJiyong Park				clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
181*54fd6939SJiyong Park				clock-names = "clcdclk", "apb_pclk";
182*54fd6939SJiyong Park				mode = "XVGA";
183*54fd6939SJiyong Park				use_dma = <0>;
184*54fd6939SJiyong Park				framebuffer = <0x18000000 0x00180000>;
185*54fd6939SJiyong Park			};
186*54fd6939SJiyong Park
187*54fd6939SJiyong Park			virtio_block@130000 {
188*54fd6939SJiyong Park				compatible = "virtio,mmio";
189*54fd6939SJiyong Park				reg = <0x130000 0x1000>;
190*54fd6939SJiyong Park				interrupts = <0x2a>;
191*54fd6939SJiyong Park			};
192*54fd6939SJiyong Park		};
193*54fd6939SJiyong Park
194*54fd6939SJiyong Park		v2m_fixed_3v3: fixedregulator@0 {
195*54fd6939SJiyong Park			compatible = "regulator-fixed";
196*54fd6939SJiyong Park			regulator-name = "3V3";
197*54fd6939SJiyong Park			regulator-min-microvolt = <3300000>;
198*54fd6939SJiyong Park			regulator-max-microvolt = <3300000>;
199*54fd6939SJiyong Park			regulator-always-on;
200*54fd6939SJiyong Park		};
201*54fd6939SJiyong Park
202*54fd6939SJiyong Park		mcc {
203*54fd6939SJiyong Park			compatible = "arm,vexpress,config-bus", "simple-bus";
204*54fd6939SJiyong Park			arm,vexpress,config-bridge = <&v2m_sysreg>;
205*54fd6939SJiyong Park
206*54fd6939SJiyong Park			v2m_oscclk1: osc@1 {
207*54fd6939SJiyong Park				/* CLCD clock */
208*54fd6939SJiyong Park				compatible = "arm,vexpress-osc";
209*54fd6939SJiyong Park				arm,vexpress-sysreg,func = <1 1>;
210*54fd6939SJiyong Park				freq-range = <23750000 63500000>;
211*54fd6939SJiyong Park				#clock-cells = <0>;
212*54fd6939SJiyong Park				clock-output-names = "v2m:oscclk1";
213*54fd6939SJiyong Park			};
214*54fd6939SJiyong Park
215*54fd6939SJiyong Park			/*
216*54fd6939SJiyong Park			 * Not supported in FVP models
217*54fd6939SJiyong Park			 *
218*54fd6939SJiyong Park			 * reset@0 {
219*54fd6939SJiyong Park			 * 	compatible = "arm,vexpress-reset";
220*54fd6939SJiyong Park			 * 	arm,vexpress-sysreg,func = <5 0>;
221*54fd6939SJiyong Park			 * };
222*54fd6939SJiyong Park			 */
223*54fd6939SJiyong Park
224*54fd6939SJiyong Park			muxfpga@0 {
225*54fd6939SJiyong Park				compatible = "arm,vexpress-muxfpga";
226*54fd6939SJiyong Park				arm,vexpress-sysreg,func = <7 0>;
227*54fd6939SJiyong Park			};
228*54fd6939SJiyong Park
229*54fd6939SJiyong Park			/*
230*54fd6939SJiyong Park			 * Not used - Superseded by PSCI sys_poweroff
231*54fd6939SJiyong Park			 *
232*54fd6939SJiyong Park			 * shutdown@0 {
233*54fd6939SJiyong Park			 * 	compatible = "arm,vexpress-shutdown";
234*54fd6939SJiyong Park			 * 	arm,vexpress-sysreg,func = <8 0>;
235*54fd6939SJiyong Park			 * };
236*54fd6939SJiyong Park			 */
237*54fd6939SJiyong Park
238*54fd6939SJiyong Park			/*
239*54fd6939SJiyong Park			 * Not used - Superseded by PSCI sys_reset
240*54fd6939SJiyong Park			 *
241*54fd6939SJiyong Park			 * reboot@0 {
242*54fd6939SJiyong Park			 * 	compatible = "arm,vexpress-reboot";
243*54fd6939SJiyong Park			 * 	arm,vexpress-sysreg,func = <9 0>;
244*54fd6939SJiyong Park			 * };
245*54fd6939SJiyong Park			 */
246*54fd6939SJiyong Park
247*54fd6939SJiyong Park			dvimode@0 {
248*54fd6939SJiyong Park				compatible = "arm,vexpress-dvimode";
249*54fd6939SJiyong Park				arm,vexpress-sysreg,func = <11 0>;
250*54fd6939SJiyong Park			};
251*54fd6939SJiyong Park		};
252*54fd6939SJiyong Park	};
253