1*54fd6939SJiyong Park// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) 2*54fd6939SJiyong Park/* 3*54fd6939SJiyong Park * Copyright (c) 2019-2020, Arm Limited. 4*54fd6939SJiyong Park */ 5*54fd6939SJiyong Park 6*54fd6939SJiyong Park/dts-v1/; 7*54fd6939SJiyong Park 8*54fd6939SJiyong Park#include "n1sdp.dtsi" 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park/ { 11*54fd6939SJiyong Park model = "Arm Neoverse N1 System Development Platform"; 12*54fd6939SJiyong Park compatible = "arm,neoverse-n1-sdp", "arm,neoverse-n1-soc"; 13*54fd6939SJiyong Park 14*54fd6939SJiyong Park aliases { 15*54fd6939SJiyong Park serial0 = &soc_uart0; 16*54fd6939SJiyong Park }; 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park chosen { 19*54fd6939SJiyong Park stdout-path = "serial0:115200n8"; 20*54fd6939SJiyong Park }; 21*54fd6939SJiyong Park 22*54fd6939SJiyong Park /* This configuration assumes that standard setup with two DIMM modules. 23*54fd6939SJiyong Park * In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory. 24*54fd6939SJiyong Park * This configuration assumes 16GB of total DRAM being populated. 25*54fd6939SJiyong Park */ 26*54fd6939SJiyong Park memory@80000000 { 27*54fd6939SJiyong Park device_type = "memory"; 28*54fd6939SJiyong Park reg = <0x00000000 0x80000000 0x0 0x7f000000>, 29*54fd6939SJiyong Park <0x00000080 0x80000000 0x3 0x80000000>; 30*54fd6939SJiyong Park numa-node-id = <0>; 31*54fd6939SJiyong Park }; 32*54fd6939SJiyong Park 33*54fd6939SJiyong Park soc_refclk60mhz: refclk60mhz { 34*54fd6939SJiyong Park compatible = "fixed-clock"; 35*54fd6939SJiyong Park #clock-cells = <0>; 36*54fd6939SJiyong Park clock-frequency = <60000000>; 37*54fd6939SJiyong Park clock-output-names = "iofpga_clk"; 38*54fd6939SJiyong Park }; 39*54fd6939SJiyong Park 40*54fd6939SJiyong Park soc_hdlcdclk: hdlcdclk { 41*54fd6939SJiyong Park compatible = "fixed-clock"; 42*54fd6939SJiyong Park #clock-cells = <0>; 43*54fd6939SJiyong Park clock-frequency = <23750000>; 44*54fd6939SJiyong Park clock-output-names = "hdlcdclk"; 45*54fd6939SJiyong Park }; 46*54fd6939SJiyong Park 47*54fd6939SJiyong Park hdlcd: hdlcd@1c050000 { 48*54fd6939SJiyong Park compatible = "arm,hdlcd"; 49*54fd6939SJiyong Park reg = <0 0x1c050000 0 0x1000>; 50*54fd6939SJiyong Park interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 51*54fd6939SJiyong Park clocks = <&soc_hdlcdclk>; 52*54fd6939SJiyong Park clock-names = "pxlclk"; 53*54fd6939SJiyong Park 54*54fd6939SJiyong Park port { 55*54fd6939SJiyong Park hdlcd0_output: endpoint { 56*54fd6939SJiyong Park remote-endpoint = <&tda998x_0_input>; 57*54fd6939SJiyong Park }; 58*54fd6939SJiyong Park }; 59*54fd6939SJiyong Park }; 60*54fd6939SJiyong Park 61*54fd6939SJiyong Park i2c@1c0f0000 { 62*54fd6939SJiyong Park compatible = "arm,versatile-i2c"; 63*54fd6939SJiyong Park reg = <0x0 0x1c0f0000 0x0 0x1000>; 64*54fd6939SJiyong Park #address-cells = <1>; 65*54fd6939SJiyong Park #size-cells = <0>; 66*54fd6939SJiyong Park clock-frequency = <400000>; 67*54fd6939SJiyong Park i2c-sda-hold-time-ns = <500>; 68*54fd6939SJiyong Park clocks = <&soc_refclk60mhz>; 69*54fd6939SJiyong Park 70*54fd6939SJiyong Park hdmi-transmitter@70 { 71*54fd6939SJiyong Park compatible = "nxp,tda998x"; 72*54fd6939SJiyong Park reg = <0x70>; 73*54fd6939SJiyong Park port { 74*54fd6939SJiyong Park tda998x_0_input: endpoint { 75*54fd6939SJiyong Park remote-endpoint = <&hdlcd0_output>; 76*54fd6939SJiyong Park }; 77*54fd6939SJiyong Park }; 78*54fd6939SJiyong Park }; 79*54fd6939SJiyong Park }; 80*54fd6939SJiyong Park}; 81*54fd6939SJiyong Park 82*54fd6939SJiyong Park&pcie_ctlr { 83*54fd6939SJiyong Park status = "okay"; 84*54fd6939SJiyong Park}; 85*54fd6939SJiyong Park 86*54fd6939SJiyong Park&ccix_pcie_ctlr { 87*54fd6939SJiyong Park status = "okay"; 88*54fd6939SJiyong Park}; 89*54fd6939SJiyong Park 90*54fd6939SJiyong Park&soc_uart0 { 91*54fd6939SJiyong Park status = "okay"; 92*54fd6939SJiyong Park}; 93