1*54fd6939SJiyong Park// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) 2*54fd6939SJiyong Park/* 3*54fd6939SJiyong Park * Copyright (c) 2019-2020, Arm Limited. 4*54fd6939SJiyong Park */ 5*54fd6939SJiyong Park 6*54fd6939SJiyong Park#include "n1sdp-single-chip.dts" 7*54fd6939SJiyong Park 8*54fd6939SJiyong Park/ { 9*54fd6939SJiyong Park cpus { 10*54fd6939SJiyong Park cpu4@100000000 { 11*54fd6939SJiyong Park compatible = "arm,neoverse-n1"; 12*54fd6939SJiyong Park reg = <0x1 0x0>; 13*54fd6939SJiyong Park device_type = "cpu"; 14*54fd6939SJiyong Park enable-method = "psci"; 15*54fd6939SJiyong Park numa-node-id = <1>; 16*54fd6939SJiyong Park }; 17*54fd6939SJiyong Park cpu5@100000100 { 18*54fd6939SJiyong Park compatible = "arm,neoverse-n1"; 19*54fd6939SJiyong Park reg = <0x1 0x00000100>; 20*54fd6939SJiyong Park device_type = "cpu"; 21*54fd6939SJiyong Park enable-method = "psci"; 22*54fd6939SJiyong Park numa-node-id = <1>; 23*54fd6939SJiyong Park }; 24*54fd6939SJiyong Park cpu6@100010000 { 25*54fd6939SJiyong Park compatible = "arm,neoverse-n1"; 26*54fd6939SJiyong Park reg = <0x1 0x00010000>; 27*54fd6939SJiyong Park device_type = "cpu"; 28*54fd6939SJiyong Park enable-method = "psci"; 29*54fd6939SJiyong Park numa-node-id = <1>; 30*54fd6939SJiyong Park }; 31*54fd6939SJiyong Park cpu7@100010100 { 32*54fd6939SJiyong Park compatible = "arm,neoverse-n1"; 33*54fd6939SJiyong Park reg = <0x1 0x00010100>; 34*54fd6939SJiyong Park device_type = "cpu"; 35*54fd6939SJiyong Park enable-method = "psci"; 36*54fd6939SJiyong Park numa-node-id = <1>; 37*54fd6939SJiyong Park }; 38*54fd6939SJiyong Park }; 39*54fd6939SJiyong Park 40*54fd6939SJiyong Park /* Remote N1SDP board address is mapped at offset 4TB. 41*54fd6939SJiyong Park * First DRAM Bank of remote N1SDP board is mapped at 4TB + 2GB. 42*54fd6939SJiyong Park */ 43*54fd6939SJiyong Park memory@40080000000 { 44*54fd6939SJiyong Park device_type = "memory"; 45*54fd6939SJiyong Park reg = <0x00000400 0x80000000 0x0 0x80000000>, 46*54fd6939SJiyong Park <0x00000480 0x80000000 0x3 0x80000000>; 47*54fd6939SJiyong Park numa-node-id = <1>; 48*54fd6939SJiyong Park }; 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park distance-map { 51*54fd6939SJiyong Park compatible = "numa-distance-map-v1"; 52*54fd6939SJiyong Park distance-matrix = <0 0 10>, 53*54fd6939SJiyong Park <0 1 20>, 54*54fd6939SJiyong Park <1 1 10>; 55*54fd6939SJiyong Park }; 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park smmu_slave_pcie: iommu@4004f400000 { 58*54fd6939SJiyong Park compatible = "arm,smmu-v3"; 59*54fd6939SJiyong Park reg = <0x400 0x4f400000 0 0x40000>; 60*54fd6939SJiyong Park interrupts = <GIC_SPI 715 IRQ_TYPE_EDGE_RISING>, 61*54fd6939SJiyong Park <GIC_SPI 716 IRQ_TYPE_EDGE_RISING>, 62*54fd6939SJiyong Park <GIC_SPI 717 IRQ_TYPE_EDGE_RISING>; 63*54fd6939SJiyong Park interrupt-names = "eventq", "cmdq-sync", "gerror"; 64*54fd6939SJiyong Park msi-parent = <&its2_slave 0>; 65*54fd6939SJiyong Park #iommu-cells = <1>; 66*54fd6939SJiyong Park dma-coherent; 67*54fd6939SJiyong Park }; 68*54fd6939SJiyong Park 69*54fd6939SJiyong Park pcie_slave_ctlr: pcie@40070000000 { 70*54fd6939SJiyong Park compatible = "arm,n1sdp-pcie"; 71*54fd6939SJiyong Park device_type = "pci"; 72*54fd6939SJiyong Park reg = <0x400 0x70000000 0 0x1200000>; 73*54fd6939SJiyong Park bus-range = <0 0xff>; 74*54fd6939SJiyong Park linux,pci-domain = <2>; 75*54fd6939SJiyong Park #address-cells = <3>; 76*54fd6939SJiyong Park #size-cells = <2>; 77*54fd6939SJiyong Park dma-coherent; 78*54fd6939SJiyong Park ranges = <0x01000000 0x00 0x00000000 0x400 0x75200000 0x00 0x00010000>, 79*54fd6939SJiyong Park <0x02000000 0x00 0x71200000 0x400 0x71200000 0x00 0x04000000>, 80*54fd6939SJiyong Park <0x42000000 0x09 0x00000000 0x409 0x00000000 0x20 0x00000000>; 81*54fd6939SJiyong Park #interrupt-cells = <1>; 82*54fd6939SJiyong Park interrupt-map-mask = <0 0 0 7>; 83*54fd6939SJiyong Park interrupt-map = <0 0 0 1 &gic 0 0 0 649 IRQ_TYPE_LEVEL_HIGH>, 84*54fd6939SJiyong Park <0 0 0 2 &gic 0 0 0 650 IRQ_TYPE_LEVEL_HIGH>, 85*54fd6939SJiyong Park <0 0 0 3 &gic 0 0 0 651 IRQ_TYPE_LEVEL_HIGH>, 86*54fd6939SJiyong Park <0 0 0 4 &gic 0 0 0 652 IRQ_TYPE_LEVEL_HIGH>; 87*54fd6939SJiyong Park msi-map = <0 &its_slave_pcie 0 0x10000>; 88*54fd6939SJiyong Park iommu-map = <0 &smmu_slave_pcie 0 0x10000>; 89*54fd6939SJiyong Park status = "okay"; 90*54fd6939SJiyong Park }; 91*54fd6939SJiyong Park 92*54fd6939SJiyong Park}; 93*54fd6939SJiyong Park 94*54fd6939SJiyong Park&gic { 95*54fd6939SJiyong Park #redistributor-regions = <2>; 96*54fd6939SJiyong Park reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 97*54fd6939SJiyong Park <0x0 0x300c0000 0 0x80000>, /* GICR */ 98*54fd6939SJiyong Park <0x400 0x300c0000 0 0x80000>; /* GICR */ 99*54fd6939SJiyong Park 100*54fd6939SJiyong Park its2_slave: its@40030060000 { 101*54fd6939SJiyong Park compatible = "arm,gic-v3-its"; 102*54fd6939SJiyong Park msi-controller; 103*54fd6939SJiyong Park #msi-cells = <1>; 104*54fd6939SJiyong Park reg = <0x400 0x30060000 0x0 0x20000>; 105*54fd6939SJiyong Park }; 106*54fd6939SJiyong Park 107*54fd6939SJiyong Park its_slave_pcie: its@400300a0000 { 108*54fd6939SJiyong Park compatible = "arm,gic-v3-its"; 109*54fd6939SJiyong Park msi-controller; 110*54fd6939SJiyong Park #msi-cells = <1>; 111*54fd6939SJiyong Park reg = <0x400 0x300a0000 0x0 0x20000>; 112*54fd6939SJiyong Park }; 113*54fd6939SJiyong Park}; 114