1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2020, Arm Limited. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <dt-bindings/interrupt-controller/arm-gic.h> 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park/ { 10*54fd6939SJiyong Park compatible = "arm,morello"; 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park interrupt-parent = <&gic>; 13*54fd6939SJiyong Park #address-cells = <2>; 14*54fd6939SJiyong Park #size-cells = <2>; 15*54fd6939SJiyong Park 16*54fd6939SJiyong Park aliases { 17*54fd6939SJiyong Park serial0 = &soc_uart0; 18*54fd6939SJiyong Park }; 19*54fd6939SJiyong Park 20*54fd6939SJiyong Park gic: interrupt-controller@2c010000 { 21*54fd6939SJiyong Park compatible = "arm,gic-600", "arm,gic-v3"; 22*54fd6939SJiyong Park #address-cells = <2>; 23*54fd6939SJiyong Park #interrupt-cells = <3>; 24*54fd6939SJiyong Park #size-cells = <2>; 25*54fd6939SJiyong Park ranges; 26*54fd6939SJiyong Park interrupt-controller; 27*54fd6939SJiyong Park }; 28*54fd6939SJiyong Park 29*54fd6939SJiyong Park pmu { 30*54fd6939SJiyong Park compatible = "arm,armv8-pmuv3"; 31*54fd6939SJiyong Park interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 32*54fd6939SJiyong Park }; 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park spe-pmu { 35*54fd6939SJiyong Park compatible = "arm,statistical-profiling-extension-v1"; 36*54fd6939SJiyong Park interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 37*54fd6939SJiyong Park }; 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park psci { 40*54fd6939SJiyong Park compatible = "arm,psci-0.2"; 41*54fd6939SJiyong Park method = "smc"; 42*54fd6939SJiyong Park }; 43*54fd6939SJiyong Park 44*54fd6939SJiyong Park timer { 45*54fd6939SJiyong Park compatible = "arm,armv8-timer"; 46*54fd6939SJiyong Park interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 47*54fd6939SJiyong Park <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 48*54fd6939SJiyong Park <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 49*54fd6939SJiyong Park <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 50*54fd6939SJiyong Park }; 51*54fd6939SJiyong Park 52*54fd6939SJiyong Park mailbox: mhu@45000000 { 53*54fd6939SJiyong Park compatible = "arm,mhu-doorbell", "arm,primecell"; 54*54fd6939SJiyong Park reg = <0x0 0x45000000 0x0 0x1000>; 55*54fd6939SJiyong Park interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 56*54fd6939SJiyong Park <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 57*54fd6939SJiyong Park interrupt-names = "mhu_lpri_rx", 58*54fd6939SJiyong Park "mhu_hpri_rx"; 59*54fd6939SJiyong Park #mbox-cells = <2>; 60*54fd6939SJiyong Park mbox-name = "ARM-MHU"; 61*54fd6939SJiyong Park clocks = <&soc_refclk100mhz>; 62*54fd6939SJiyong Park clock-names = "apb_pclk"; 63*54fd6939SJiyong Park }; 64*54fd6939SJiyong Park 65*54fd6939SJiyong Park sram: sram@45200000 { 66*54fd6939SJiyong Park compatible = "mmio-sram"; 67*54fd6939SJiyong Park reg = <0x0 0x45200000 0x0 0x8000>; 68*54fd6939SJiyong Park 69*54fd6939SJiyong Park #address-cells = <1>; 70*54fd6939SJiyong Park #size-cells = <1>; 71*54fd6939SJiyong Park ranges = <0 0x0 0x45200000 0x8000>; 72*54fd6939SJiyong Park 73*54fd6939SJiyong Park cpu_scp_hpri0: scp-shmem@0 { 74*54fd6939SJiyong Park compatible = "arm,scmi-shmem"; 75*54fd6939SJiyong Park reg = <0x0 0x80>; 76*54fd6939SJiyong Park }; 77*54fd6939SJiyong Park 78*54fd6939SJiyong Park cpu_scp_hpri1: scp-shmem@80 { 79*54fd6939SJiyong Park compatible = "arm,scmi-shmem"; 80*54fd6939SJiyong Park reg = <0x80 0x80>; 81*54fd6939SJiyong Park }; 82*54fd6939SJiyong Park }; 83*54fd6939SJiyong Park 84*54fd6939SJiyong Park soc_refclk100mhz: refclk100mhz { 85*54fd6939SJiyong Park compatible = "fixed-clock"; 86*54fd6939SJiyong Park #clock-cells = <0>; 87*54fd6939SJiyong Park clock-frequency = <100000000>; 88*54fd6939SJiyong Park clock-output-names = "apb_pclk"; 89*54fd6939SJiyong Park }; 90*54fd6939SJiyong Park 91*54fd6939SJiyong Park soc_uartclk: uartclk { 92*54fd6939SJiyong Park compatible = "fixed-clock"; 93*54fd6939SJiyong Park #clock-cells = <0>; 94*54fd6939SJiyong Park clock-frequency = <50000000>; 95*54fd6939SJiyong Park clock-output-names = "uartclk"; 96*54fd6939SJiyong Park }; 97*54fd6939SJiyong Park 98*54fd6939SJiyong Park soc_uart0: uart@2a400000 { 99*54fd6939SJiyong Park compatible = "arm,pl011", "arm,primecell"; 100*54fd6939SJiyong Park reg = <0x0 0x2a400000 0x0 0x1000>; 101*54fd6939SJiyong Park interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 102*54fd6939SJiyong Park clocks = <&soc_uartclk>, <&soc_refclk100mhz>; 103*54fd6939SJiyong Park clock-names = "uartclk", "apb_pclk"; 104*54fd6939SJiyong Park status = "okay"; 105*54fd6939SJiyong Park }; 106*54fd6939SJiyong Park}; 107