xref: /aosp_15_r20/external/arm-trusted-firmware/fdts/fvp-foundation-motherboard.dtsi (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1*54fd6939SJiyong Park/*
2*54fd6939SJiyong Park * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park	motherboard {
8*54fd6939SJiyong Park		arm,v2m-memory-map = "rs1";
9*54fd6939SJiyong Park		compatible = "arm,vexpress,v2m-p1", "simple-bus";
10*54fd6939SJiyong Park		#address-cells = <2>; /* SMB chipselect number and offset */
11*54fd6939SJiyong Park		#size-cells = <1>;
12*54fd6939SJiyong Park		ranges;
13*54fd6939SJiyong Park
14*54fd6939SJiyong Park		ethernet@2,02000000 {
15*54fd6939SJiyong Park			compatible = "smsc,lan91c111";
16*54fd6939SJiyong Park			reg = <2 0x02000000 0x10000>;
17*54fd6939SJiyong Park			interrupts = <0 15 4>;
18*54fd6939SJiyong Park		};
19*54fd6939SJiyong Park
20*54fd6939SJiyong Park		v2m_clk24mhz: clk24mhz {
21*54fd6939SJiyong Park			compatible = "fixed-clock";
22*54fd6939SJiyong Park			#clock-cells = <0>;
23*54fd6939SJiyong Park			clock-frequency = <24000000>;
24*54fd6939SJiyong Park			clock-output-names = "v2m:clk24mhz";
25*54fd6939SJiyong Park		};
26*54fd6939SJiyong Park
27*54fd6939SJiyong Park		v2m_refclk1mhz: refclk1mhz {
28*54fd6939SJiyong Park			compatible = "fixed-clock";
29*54fd6939SJiyong Park			#clock-cells = <0>;
30*54fd6939SJiyong Park			clock-frequency = <1000000>;
31*54fd6939SJiyong Park			clock-output-names = "v2m:refclk1mhz";
32*54fd6939SJiyong Park		};
33*54fd6939SJiyong Park
34*54fd6939SJiyong Park		v2m_refclk32khz: refclk32khz {
35*54fd6939SJiyong Park			compatible = "fixed-clock";
36*54fd6939SJiyong Park			#clock-cells = <0>;
37*54fd6939SJiyong Park			clock-frequency = <32768>;
38*54fd6939SJiyong Park			clock-output-names = "v2m:refclk32khz";
39*54fd6939SJiyong Park		};
40*54fd6939SJiyong Park
41*54fd6939SJiyong Park		iofpga@3,00000000 {
42*54fd6939SJiyong Park			compatible = "arm,amba-bus", "simple-bus";
43*54fd6939SJiyong Park			#address-cells = <1>;
44*54fd6939SJiyong Park			#size-cells = <1>;
45*54fd6939SJiyong Park			ranges = <0 3 0 0x200000>;
46*54fd6939SJiyong Park
47*54fd6939SJiyong Park			v2m_sysreg: sysreg@10000 {
48*54fd6939SJiyong Park				compatible = "arm,vexpress-sysreg";
49*54fd6939SJiyong Park				reg = <0x010000 0x1000>;
50*54fd6939SJiyong Park				gpio-controller;
51*54fd6939SJiyong Park				#gpio-cells = <2>;
52*54fd6939SJiyong Park			};
53*54fd6939SJiyong Park
54*54fd6939SJiyong Park			v2m_sysctl: sysctl@20000 {
55*54fd6939SJiyong Park				compatible = "arm,sp810", "arm,primecell";
56*54fd6939SJiyong Park				reg = <0x020000 0x1000>;
57*54fd6939SJiyong Park				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
58*54fd6939SJiyong Park				clock-names = "refclk", "timclk", "apb_pclk";
59*54fd6939SJiyong Park				#clock-cells = <1>;
60*54fd6939SJiyong Park				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
61*54fd6939SJiyong Park			};
62*54fd6939SJiyong Park
63*54fd6939SJiyong Park			v2m_serial0: uart@90000 {
64*54fd6939SJiyong Park				compatible = "arm,pl011", "arm,primecell";
65*54fd6939SJiyong Park				reg = <0x090000 0x1000>;
66*54fd6939SJiyong Park				interrupts = <0 5 4>;
67*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
68*54fd6939SJiyong Park				clock-names = "uartclk", "apb_pclk";
69*54fd6939SJiyong Park			};
70*54fd6939SJiyong Park
71*54fd6939SJiyong Park			v2m_serial1: uart@a0000 {
72*54fd6939SJiyong Park				compatible = "arm,pl011", "arm,primecell";
73*54fd6939SJiyong Park				reg = <0x0a0000 0x1000>;
74*54fd6939SJiyong Park				interrupts = <0 6 4>;
75*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
76*54fd6939SJiyong Park				clock-names = "uartclk", "apb_pclk";
77*54fd6939SJiyong Park			};
78*54fd6939SJiyong Park
79*54fd6939SJiyong Park			v2m_serial2: uart@b0000 {
80*54fd6939SJiyong Park				compatible = "arm,pl011", "arm,primecell";
81*54fd6939SJiyong Park				reg = <0x0b0000 0x1000>;
82*54fd6939SJiyong Park				interrupts = <0 7 4>;
83*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
84*54fd6939SJiyong Park				clock-names = "uartclk", "apb_pclk";
85*54fd6939SJiyong Park			};
86*54fd6939SJiyong Park
87*54fd6939SJiyong Park			v2m_serial3: uart@c0000 {
88*54fd6939SJiyong Park				compatible = "arm,pl011", "arm,primecell";
89*54fd6939SJiyong Park				reg = <0x0c0000 0x1000>;
90*54fd6939SJiyong Park				interrupts = <0 8 4>;
91*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
92*54fd6939SJiyong Park				clock-names = "uartclk", "apb_pclk";
93*54fd6939SJiyong Park			};
94*54fd6939SJiyong Park
95*54fd6939SJiyong Park			wdt@f0000 {
96*54fd6939SJiyong Park				compatible = "arm,sp805", "arm,primecell";
97*54fd6939SJiyong Park				reg = <0x0f0000 0x1000>;
98*54fd6939SJiyong Park				interrupts = <0 0 4>;
99*54fd6939SJiyong Park				clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
100*54fd6939SJiyong Park				clock-names = "wdogclk", "apb_pclk";
101*54fd6939SJiyong Park			};
102*54fd6939SJiyong Park
103*54fd6939SJiyong Park			v2m_timer01: timer@110000 {
104*54fd6939SJiyong Park				compatible = "arm,sp804", "arm,primecell";
105*54fd6939SJiyong Park				reg = <0x110000 0x1000>;
106*54fd6939SJiyong Park				interrupts = <0 2 4>;
107*54fd6939SJiyong Park				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
108*54fd6939SJiyong Park				clock-names = "timclken1", "timclken2", "apb_pclk";
109*54fd6939SJiyong Park			};
110*54fd6939SJiyong Park
111*54fd6939SJiyong Park			v2m_timer23: timer@120000 {
112*54fd6939SJiyong Park				compatible = "arm,sp804", "arm,primecell";
113*54fd6939SJiyong Park				reg = <0x120000 0x1000>;
114*54fd6939SJiyong Park				interrupts = <0 3 4>;
115*54fd6939SJiyong Park				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
116*54fd6939SJiyong Park				clock-names = "timclken1", "timclken2", "apb_pclk";
117*54fd6939SJiyong Park			};
118*54fd6939SJiyong Park
119*54fd6939SJiyong Park			rtc@170000 {
120*54fd6939SJiyong Park				compatible = "arm,pl031", "arm,primecell";
121*54fd6939SJiyong Park				reg = <0x170000 0x1000>;
122*54fd6939SJiyong Park				interrupts = <0 4 4>;
123*54fd6939SJiyong Park				clocks = <&v2m_clk24mhz>;
124*54fd6939SJiyong Park				clock-names = "apb_pclk";
125*54fd6939SJiyong Park			};
126*54fd6939SJiyong Park
127*54fd6939SJiyong Park			virtio_block@130000 {
128*54fd6939SJiyong Park				compatible = "virtio,mmio";
129*54fd6939SJiyong Park				reg = <0x130000 0x1000>;
130*54fd6939SJiyong Park				interrupts = <0 0x2a 4>;
131*54fd6939SJiyong Park			};
132*54fd6939SJiyong Park		};
133*54fd6939SJiyong Park
134*54fd6939SJiyong Park		v2m_fixed_3v3: fixedregulator@0 {
135*54fd6939SJiyong Park			compatible = "regulator-fixed";
136*54fd6939SJiyong Park			regulator-name = "3V3";
137*54fd6939SJiyong Park			regulator-min-microvolt = <3300000>;
138*54fd6939SJiyong Park			regulator-max-microvolt = <3300000>;
139*54fd6939SJiyong Park			regulator-always-on;
140*54fd6939SJiyong Park		};
141*54fd6939SJiyong Park
142*54fd6939SJiyong Park
143*54fd6939SJiyong Park		mcc {
144*54fd6939SJiyong Park			compatible = "arm,vexpress,config-bus", "simple-bus";
145*54fd6939SJiyong Park			arm,vexpress,config-bridge = <&v2m_sysreg>;
146*54fd6939SJiyong Park
147*54fd6939SJiyong Park			/*
148*54fd6939SJiyong Park			 * Not supported in FVP models
149*54fd6939SJiyong Park			 *
150*54fd6939SJiyong Park			 * reset@0 {
151*54fd6939SJiyong Park			 * 	compatible = "arm,vexpress-reset";
152*54fd6939SJiyong Park			 * 	arm,vexpress-sysreg,func = <5 0>;
153*54fd6939SJiyong Park			 * };
154*54fd6939SJiyong Park			 */
155*54fd6939SJiyong Park
156*54fd6939SJiyong Park			muxfpga@0 {
157*54fd6939SJiyong Park				compatible = "arm,vexpress-muxfpga";
158*54fd6939SJiyong Park				arm,vexpress-sysreg,func = <7 0>;
159*54fd6939SJiyong Park			};
160*54fd6939SJiyong Park
161*54fd6939SJiyong Park			/*
162*54fd6939SJiyong Park			 * Not used - Superseded by PSCI sys_poweroff
163*54fd6939SJiyong Park			 *
164*54fd6939SJiyong Park			 * shutdown@0 {
165*54fd6939SJiyong Park			 * 	compatible = "arm,vexpress-shutdown";
166*54fd6939SJiyong Park			 * 	arm,vexpress-sysreg,func = <8 0>;
167*54fd6939SJiyong Park			 * };
168*54fd6939SJiyong Park			 */
169*54fd6939SJiyong Park
170*54fd6939SJiyong Park			/*
171*54fd6939SJiyong Park			 * Not used - Superseded by PSCI sys_reset
172*54fd6939SJiyong Park			 *
173*54fd6939SJiyong Park			 * reboot@0 {
174*54fd6939SJiyong Park			 * 	compatible = "arm,vexpress-reboot";
175*54fd6939SJiyong Park			 * 	arm,vexpress-sysreg,func = <9 0>;
176*54fd6939SJiyong Park			 * };
177*54fd6939SJiyong Park			 */
178*54fd6939SJiyong Park
179*54fd6939SJiyong Park			dvimode@0 {
180*54fd6939SJiyong Park				compatible = "arm,vexpress-dvimode";
181*54fd6939SJiyong Park				arm,vexpress-sysreg,func = <11 0>;
182*54fd6939SJiyong Park			};
183*54fd6939SJiyong Park		};
184*54fd6939SJiyong Park	};
185