1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2020, Arm Limited. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <dt-bindings/interrupt-controller/arm-gic.h> 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park/ { 10*54fd6939SJiyong Park compatible = "arm,Corstone-700"; 11*54fd6939SJiyong Park interrupt-parent = <&gic>; 12*54fd6939SJiyong Park #address-cells = <1>; 13*54fd6939SJiyong Park #size-cells = <1>; 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park chosen { }; 16*54fd6939SJiyong Park 17*54fd6939SJiyong Park cpus { 18*54fd6939SJiyong Park #address-cells = <1>; 19*54fd6939SJiyong Park #size-cells = <0>; 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park cpu@0 { 22*54fd6939SJiyong Park device_type = "cpu"; 23*54fd6939SJiyong Park compatible = "arm,armv8"; 24*54fd6939SJiyong Park reg = <0>; 25*54fd6939SJiyong Park next-level-cache = <&L2_0>; 26*54fd6939SJiyong Park }; 27*54fd6939SJiyong Park }; 28*54fd6939SJiyong Park 29*54fd6939SJiyong Park memory@80000000 { 30*54fd6939SJiyong Park device_type = "memory"; 31*54fd6939SJiyong Park reg = <0x80000000 0x80000000>; 32*54fd6939SJiyong Park }; 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park gic: interrupt-controller@1c000000 { 35*54fd6939SJiyong Park compatible = "arm,gic-400"; 36*54fd6939SJiyong Park #interrupt-cells = <3>; 37*54fd6939SJiyong Park #address-cells = <0>; 38*54fd6939SJiyong Park interrupt-controller; 39*54fd6939SJiyong Park reg = <0x1c010000 0x1000>, 40*54fd6939SJiyong Park <0x1c02f000 0x2000>, 41*54fd6939SJiyong Park <0x1c04f000 0x1000>, 42*54fd6939SJiyong Park <0x1c06f000 0x2000>; 43*54fd6939SJiyong Park interrupts = <1 9 0xf08>; 44*54fd6939SJiyong Park }; 45*54fd6939SJiyong Park 46*54fd6939SJiyong Park L2_0: l2-cache0 { 47*54fd6939SJiyong Park compatible = "cache"; 48*54fd6939SJiyong Park }; 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park refclk100mhz: refclk100mhz { 51*54fd6939SJiyong Park compatible = "fixed-clock"; 52*54fd6939SJiyong Park #clock-cells = <0>; 53*54fd6939SJiyong Park clock-frequency = <100000000>; 54*54fd6939SJiyong Park clock-output-names = "apb_pclk"; 55*54fd6939SJiyong Park }; 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park smbclk: refclk24mhzx2 { 58*54fd6939SJiyong Park /* Reference 24MHz clock x 2 */ 59*54fd6939SJiyong Park compatible = "fixed-clock"; 60*54fd6939SJiyong Park #clock-cells = <0>; 61*54fd6939SJiyong Park clock-frequency = <48000000>; 62*54fd6939SJiyong Park clock-output-names = "smclk"; 63*54fd6939SJiyong Park }; 64*54fd6939SJiyong Park 65*54fd6939SJiyong Park uartclk: uartclk { 66*54fd6939SJiyong Park /* UART clock - 32MHz */ 67*54fd6939SJiyong Park compatible = "fixed-clock"; 68*54fd6939SJiyong Park #clock-cells = <0>; 69*54fd6939SJiyong Park clock-frequency = <32000000>; 70*54fd6939SJiyong Park clock-output-names = "uartclk"; 71*54fd6939SJiyong Park }; 72*54fd6939SJiyong Park 73*54fd6939SJiyong Park serial0: uart@1a510000 { 74*54fd6939SJiyong Park compatible = "arm,pl011", "arm,primecell"; 75*54fd6939SJiyong Park reg = <0x1a510000 0x1000>; 76*54fd6939SJiyong Park interrupt-parent = <&gic>; 77*54fd6939SJiyong Park interrupts = <0 19 4>; 78*54fd6939SJiyong Park clocks = <&uartclk>, <&refclk100mhz>; 79*54fd6939SJiyong Park clock-names = "uartclk", "apb_pclk"; 80*54fd6939SJiyong Park }; 81*54fd6939SJiyong Park 82*54fd6939SJiyong Park serial1: uart@1a520000 { 83*54fd6939SJiyong Park compatible = "arm,pl011", "arm,primecell"; 84*54fd6939SJiyong Park reg = <0x1a520000 0x1000>; 85*54fd6939SJiyong Park interrupt-parent = <&gic>; 86*54fd6939SJiyong Park interrupts = <0 20 4>; 87*54fd6939SJiyong Park clocks = <&uartclk>, <&refclk100mhz>; 88*54fd6939SJiyong Park clock-names = "uartclk", "apb_pclk"; 89*54fd6939SJiyong Park }; 90*54fd6939SJiyong Park 91*54fd6939SJiyong Park timer { 92*54fd6939SJiyong Park compatible = "arm,armv8-timer"; 93*54fd6939SJiyong Park interrupts = <1 13 0xf08>, 94*54fd6939SJiyong Park <1 14 0xf08>, 95*54fd6939SJiyong Park <1 11 0xf08>, 96*54fd6939SJiyong Park <1 10 0xf08>; 97*54fd6939SJiyong Park }; 98*54fd6939SJiyong Park 99*54fd6939SJiyong Park refclk: refclk@1a220000 { 100*54fd6939SJiyong Park compatible = "arm,armv7-timer-mem"; 101*54fd6939SJiyong Park reg = <0x1a220000 0x1000>; 102*54fd6939SJiyong Park #address-cells = <1>; 103*54fd6939SJiyong Park #size-cells = <1>; 104*54fd6939SJiyong Park ranges; 105*54fd6939SJiyong Park 106*54fd6939SJiyong Park frame@1a230000 { 107*54fd6939SJiyong Park frame-number = <0>; 108*54fd6939SJiyong Park interrupts = <0 2 0xf04>; 109*54fd6939SJiyong Park reg = <0x1a230000 0x1000>; 110*54fd6939SJiyong Park }; 111*54fd6939SJiyong Park }; 112*54fd6939SJiyong Park 113*54fd6939SJiyong Park mbox_es0mhu0: mhu@1b000000 { 114*54fd6939SJiyong Park compatible = "arm,mhuv2","arm,primecell"; 115*54fd6939SJiyong Park reg = <0x1b000000 0x1000>, 116*54fd6939SJiyong Park <0x1b010000 0x1000>; 117*54fd6939SJiyong Park clocks = <&refclk100mhz>; 118*54fd6939SJiyong Park clock-names = "apb_pclk"; 119*54fd6939SJiyong Park interrupts = <0 12 4>; 120*54fd6939SJiyong Park interrupt-names = "mhu_rx"; 121*54fd6939SJiyong Park #mbox-cells = <1>; 122*54fd6939SJiyong Park mbox-name = "arm-es0-mhu0"; 123*54fd6939SJiyong Park }; 124*54fd6939SJiyong Park 125*54fd6939SJiyong Park mbox_es0mhu1: mhu@1b020000 { 126*54fd6939SJiyong Park compatible = "arm,mhuv2","arm,primecell"; 127*54fd6939SJiyong Park reg = <0x1b020000 0x1000>, 128*54fd6939SJiyong Park <0x1b030000 0x1000>; 129*54fd6939SJiyong Park clocks = <&refclk100mhz>; 130*54fd6939SJiyong Park clock-names = "apb_pclk"; 131*54fd6939SJiyong Park interrupts = <0 47 4>; 132*54fd6939SJiyong Park interrupt-names = "mhu_rx"; 133*54fd6939SJiyong Park #mbox-cells = <1>; 134*54fd6939SJiyong Park mbox-name = "arm-es0-mhu1"; 135*54fd6939SJiyong Park }; 136*54fd6939SJiyong Park 137*54fd6939SJiyong Park mbox_semhu1: mhu@1b820000 { 138*54fd6939SJiyong Park compatible = "arm,mhuv2","arm,primecell"; 139*54fd6939SJiyong Park reg = <0x1b820000 0x1000>, 140*54fd6939SJiyong Park <0x1b830000 0x1000>; 141*54fd6939SJiyong Park clocks = <&refclk100mhz>; 142*54fd6939SJiyong Park clock-names = "apb_pclk"; 143*54fd6939SJiyong Park interrupts = <0 45 4>; 144*54fd6939SJiyong Park interrupt-names = "mhu_rx"; 145*54fd6939SJiyong Park #mbox-cells = <1>; 146*54fd6939SJiyong Park mbox-name = "arm-se-mhu1"; 147*54fd6939SJiyong Park }; 148*54fd6939SJiyong Park 149*54fd6939SJiyong Park client { 150*54fd6939SJiyong Park compatible = "arm,client"; 151*54fd6939SJiyong Park mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>; 152*54fd6939SJiyong Park mbox-names = "es0mhu0", "es0mhu1", "semhu1"; 153*54fd6939SJiyong Park }; 154*54fd6939SJiyong Park 155*54fd6939SJiyong Park extsys0: extsys@1A010310 { 156*54fd6939SJiyong Park compatible = "arm,extsys_ctrl"; 157*54fd6939SJiyong Park reg = <0x1A010310 0x4>, 158*54fd6939SJiyong Park <0x1A010314 0x4>; 159*54fd6939SJiyong Park reg-names = "rstreg", "streg"; 160*54fd6939SJiyong Park }; 161*54fd6939SJiyong Park}; 162