1*54fd6939SJiyong Park// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) 2*54fd6939SJiyong Park/* 3*54fd6939SJiyong Park * Copyright (c) 2020, Arm Limited. All rights reserved. 4*54fd6939SJiyong Park * 5*54fd6939SJiyong Park * Devicetree for the Arm Ltd. FPGA platform 6*54fd6939SJiyong Park * Number and kind of CPU cores differs from image to image, so the 7*54fd6939SJiyong Park * topology is auto-detected by BL31, and the /cpus node is created and 8*54fd6939SJiyong Park * populated accordingly at runtime. 9*54fd6939SJiyong Park */ 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park#include <dt-bindings/interrupt-controller/arm-gic.h> 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park/dts-v1/; 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park/ { 16*54fd6939SJiyong Park model = "ARM FPGA"; 17*54fd6939SJiyong Park compatible = "arm,fpga", "arm,vexpress"; 18*54fd6939SJiyong Park interrupt-parent = <&gic>; 19*54fd6939SJiyong Park #address-cells = <2>; 20*54fd6939SJiyong Park #size-cells = <2>; 21*54fd6939SJiyong Park 22*54fd6939SJiyong Park aliases { 23*54fd6939SJiyong Park serial0 = &dbg_uart; 24*54fd6939SJiyong Park }; 25*54fd6939SJiyong Park 26*54fd6939SJiyong Park chosen { 27*54fd6939SJiyong Park stdout-path = "serial0:38400n8"; 28*54fd6939SJiyong Park bootargs = "console=ttyAMA0,38400n8 earlycon"; 29*54fd6939SJiyong Park /* Allow to upload a generous 100MB initrd payload. */ 30*54fd6939SJiyong Park linux,initrd-start = <0x0 0x84000000>; 31*54fd6939SJiyong Park linux,initrd-end = <0x0 0x8a400000>; 32*54fd6939SJiyong Park }; 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park /* /cpus node will be added by BL31 at runtime. */ 35*54fd6939SJiyong Park 36*54fd6939SJiyong Park psci { 37*54fd6939SJiyong Park compatible = "arm,psci-0.2"; 38*54fd6939SJiyong Park method = "smc"; 39*54fd6939SJiyong Park }; 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park timer { 42*54fd6939SJiyong Park compatible = "arm,armv8-timer"; 43*54fd6939SJiyong Park interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 44*54fd6939SJiyong Park <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 45*54fd6939SJiyong Park <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 46*54fd6939SJiyong Park <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 47*54fd6939SJiyong Park }; 48*54fd6939SJiyong Park 49*54fd6939SJiyong Park pmu { 50*54fd6939SJiyong Park compatible = "arm,armv8-pmuv3"; 51*54fd6939SJiyong Park interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 52*54fd6939SJiyong Park }; 53*54fd6939SJiyong Park 54*54fd6939SJiyong Park /* This node will be removed at runtime on cores without SPE. */ 55*54fd6939SJiyong Park spe-pmu { 56*54fd6939SJiyong Park compatible = "arm,statistical-profiling-extension-v1"; 57*54fd6939SJiyong Park interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 58*54fd6939SJiyong Park }; 59*54fd6939SJiyong Park 60*54fd6939SJiyong Park memory@80000000 { 61*54fd6939SJiyong Park device_type = "memory"; 62*54fd6939SJiyong Park reg = <0x0 0x80000000 0x0 0x80000000>, 63*54fd6939SJiyong Park <0x8 0x80000000 0x1 0x80000000>; 64*54fd6939SJiyong Park }; 65*54fd6939SJiyong Park 66*54fd6939SJiyong Park 67*54fd6939SJiyong Park bus_refclk: refclk { 68*54fd6939SJiyong Park compatible = "fixed-clock"; 69*54fd6939SJiyong Park #clock-cells = <0>; 70*54fd6939SJiyong Park clock-frequency = <100000000>; 71*54fd6939SJiyong Park clock-output-names = "apb_pclk"; 72*54fd6939SJiyong Park }; 73*54fd6939SJiyong Park 74*54fd6939SJiyong Park uartclk: baudclock { 75*54fd6939SJiyong Park compatible = "fixed-clock"; 76*54fd6939SJiyong Park #clock-cells = <0>; 77*54fd6939SJiyong Park clock-frequency = <10000000>; 78*54fd6939SJiyong Park clock-output-names = "uartclk"; 79*54fd6939SJiyong Park }; 80*54fd6939SJiyong Park 81*54fd6939SJiyong Park dbg_uart: serial@7ff80000 { 82*54fd6939SJiyong Park compatible = "arm,pl011", "arm,primecell"; 83*54fd6939SJiyong Park reg = <0x0 0x7ff80000 0x0 0x00001000>; 84*54fd6939SJiyong Park interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>; 85*54fd6939SJiyong Park clocks = <&uartclk>, <&bus_refclk>; 86*54fd6939SJiyong Park clock-names = "uartclk", "apb_pclk"; 87*54fd6939SJiyong Park }; 88*54fd6939SJiyong Park 89*54fd6939SJiyong Park gic: interrupt-controller@30000000 { 90*54fd6939SJiyong Park compatible = "arm,gic-v3"; 91*54fd6939SJiyong Park #address-cells = <2>; 92*54fd6939SJiyong Park #interrupt-cells = <3>; 93*54fd6939SJiyong Park #size-cells = <2>; 94*54fd6939SJiyong Park ranges; 95*54fd6939SJiyong Park interrupt-controller; 96*54fd6939SJiyong Park reg = <0x0 0x30000000 0x0 0x00010000>, /* GICD */ 97*54fd6939SJiyong Park /* The GICR size will be adjusted at runtime to match the cores. */ 98*54fd6939SJiyong Park <0x0 0x30040000 0x0 0x00020000>; /* GICR for one core */ 99*54fd6939SJiyong Park interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 100*54fd6939SJiyong Park 101*54fd6939SJiyong Park its: msi-controller@30040000 { 102*54fd6939SJiyong Park compatible = "arm,gic-v3-its"; 103*54fd6939SJiyong Park reg = <0x0 0x30040000 0x0 0x40000>; 104*54fd6939SJiyong Park #msi-cells = <1>; 105*54fd6939SJiyong Park msi-controller; 106*54fd6939SJiyong Park }; 107*54fd6939SJiyong Park }; 108*54fd6939SJiyong Park}; 109