1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park #ifndef PFC_REGS_H 7*54fd6939SJiyong Park #define PFC_REGS_H 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park /* GPIO base address */ 10*54fd6939SJiyong Park #define GPIO_BASE (0xE6050000U) 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /* GPIO registers */ 13*54fd6939SJiyong Park #define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U) 14*54fd6939SJiyong Park #define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U) 15*54fd6939SJiyong Park #define GPIO_OUTDT0 (GPIO_BASE + 0x0008U) 16*54fd6939SJiyong Park #define GPIO_INDT0 (GPIO_BASE + 0x000CU) 17*54fd6939SJiyong Park #define GPIO_INTDT0 (GPIO_BASE + 0x0010U) 18*54fd6939SJiyong Park #define GPIO_INTCLR0 (GPIO_BASE + 0x0014U) 19*54fd6939SJiyong Park #define GPIO_INTMSK0 (GPIO_BASE + 0x0018U) 20*54fd6939SJiyong Park #define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU) 21*54fd6939SJiyong Park #define GPIO_POSNEG0 (GPIO_BASE + 0x0020U) 22*54fd6939SJiyong Park #define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U) 23*54fd6939SJiyong Park #define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U) 24*54fd6939SJiyong Park #define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U) 25*54fd6939SJiyong Park #define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU) 26*54fd6939SJiyong Park #define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U) 27*54fd6939SJiyong Park #define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U) 28*54fd6939SJiyong Park #define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U) 29*54fd6939SJiyong Park #define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU) 30*54fd6939SJiyong Park #define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U) 31*54fd6939SJiyong Park #define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U) 32*54fd6939SJiyong Park #define GPIO_OUTDT1 (GPIO_BASE + 0x1008U) 33*54fd6939SJiyong Park #define GPIO_INDT1 (GPIO_BASE + 0x100CU) 34*54fd6939SJiyong Park #define GPIO_INTDT1 (GPIO_BASE + 0x1010U) 35*54fd6939SJiyong Park #define GPIO_INTCLR1 (GPIO_BASE + 0x1014U) 36*54fd6939SJiyong Park #define GPIO_INTMSK1 (GPIO_BASE + 0x1018U) 37*54fd6939SJiyong Park #define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU) 38*54fd6939SJiyong Park #define GPIO_POSNEG1 (GPIO_BASE + 0x1020U) 39*54fd6939SJiyong Park #define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U) 40*54fd6939SJiyong Park #define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U) 41*54fd6939SJiyong Park #define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U) 42*54fd6939SJiyong Park #define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU) 43*54fd6939SJiyong Park #define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U) 44*54fd6939SJiyong Park #define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U) 45*54fd6939SJiyong Park #define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U) 46*54fd6939SJiyong Park #define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU) 47*54fd6939SJiyong Park #define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U) 48*54fd6939SJiyong Park #define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U) 49*54fd6939SJiyong Park #define GPIO_OUTDT2 (GPIO_BASE + 0x2008U) 50*54fd6939SJiyong Park #define GPIO_INDT2 (GPIO_BASE + 0x200CU) 51*54fd6939SJiyong Park #define GPIO_INTDT2 (GPIO_BASE + 0x2010U) 52*54fd6939SJiyong Park #define GPIO_INTCLR2 (GPIO_BASE + 0x2014U) 53*54fd6939SJiyong Park #define GPIO_INTMSK2 (GPIO_BASE + 0x2018U) 54*54fd6939SJiyong Park #define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU) 55*54fd6939SJiyong Park #define GPIO_POSNEG2 (GPIO_BASE + 0x2020U) 56*54fd6939SJiyong Park #define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U) 57*54fd6939SJiyong Park #define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U) 58*54fd6939SJiyong Park #define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U) 59*54fd6939SJiyong Park #define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU) 60*54fd6939SJiyong Park #define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U) 61*54fd6939SJiyong Park #define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U) 62*54fd6939SJiyong Park #define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U) 63*54fd6939SJiyong Park #define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU) 64*54fd6939SJiyong Park #define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U) 65*54fd6939SJiyong Park #define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U) 66*54fd6939SJiyong Park #define GPIO_OUTDT3 (GPIO_BASE + 0x3008U) 67*54fd6939SJiyong Park #define GPIO_INDT3 (GPIO_BASE + 0x300CU) 68*54fd6939SJiyong Park #define GPIO_INTDT3 (GPIO_BASE + 0x3010U) 69*54fd6939SJiyong Park #define GPIO_INTCLR3 (GPIO_BASE + 0x3014U) 70*54fd6939SJiyong Park #define GPIO_INTMSK3 (GPIO_BASE + 0x3018U) 71*54fd6939SJiyong Park #define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU) 72*54fd6939SJiyong Park #define GPIO_POSNEG3 (GPIO_BASE + 0x3020U) 73*54fd6939SJiyong Park #define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U) 74*54fd6939SJiyong Park #define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U) 75*54fd6939SJiyong Park #define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U) 76*54fd6939SJiyong Park #define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU) 77*54fd6939SJiyong Park #define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U) 78*54fd6939SJiyong Park #define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U) 79*54fd6939SJiyong Park #define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U) 80*54fd6939SJiyong Park #define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU) 81*54fd6939SJiyong Park #define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U) 82*54fd6939SJiyong Park #define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U) 83*54fd6939SJiyong Park #define GPIO_OUTDT4 (GPIO_BASE + 0x4008U) 84*54fd6939SJiyong Park #define GPIO_INDT4 (GPIO_BASE + 0x400CU) 85*54fd6939SJiyong Park #define GPIO_INTDT4 (GPIO_BASE + 0x4010U) 86*54fd6939SJiyong Park #define GPIO_INTCLR4 (GPIO_BASE + 0x4014U) 87*54fd6939SJiyong Park #define GPIO_INTMSK4 (GPIO_BASE + 0x4018U) 88*54fd6939SJiyong Park #define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU) 89*54fd6939SJiyong Park #define GPIO_POSNEG4 (GPIO_BASE + 0x4020U) 90*54fd6939SJiyong Park #define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U) 91*54fd6939SJiyong Park #define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U) 92*54fd6939SJiyong Park #define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U) 93*54fd6939SJiyong Park #define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU) 94*54fd6939SJiyong Park #define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U) 95*54fd6939SJiyong Park #define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U) 96*54fd6939SJiyong Park #define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U) 97*54fd6939SJiyong Park #define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU) 98*54fd6939SJiyong Park #define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U) 99*54fd6939SJiyong Park #define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U) 100*54fd6939SJiyong Park #define GPIO_OUTDT5 (GPIO_BASE + 0x5008U) 101*54fd6939SJiyong Park #define GPIO_INDT5 (GPIO_BASE + 0x500CU) 102*54fd6939SJiyong Park #define GPIO_INTDT5 (GPIO_BASE + 0x5010U) 103*54fd6939SJiyong Park #define GPIO_INTCLR5 (GPIO_BASE + 0x5014U) 104*54fd6939SJiyong Park #define GPIO_INTMSK5 (GPIO_BASE + 0x5018U) 105*54fd6939SJiyong Park #define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU) 106*54fd6939SJiyong Park #define GPIO_POSNEG5 (GPIO_BASE + 0x5020U) 107*54fd6939SJiyong Park #define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U) 108*54fd6939SJiyong Park #define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U) 109*54fd6939SJiyong Park #define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U) 110*54fd6939SJiyong Park #define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU) 111*54fd6939SJiyong Park #define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U) 112*54fd6939SJiyong Park #define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U) 113*54fd6939SJiyong Park #define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U) 114*54fd6939SJiyong Park #define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU) 115*54fd6939SJiyong Park #define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U) 116*54fd6939SJiyong Park #define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U) 117*54fd6939SJiyong Park #define GPIO_OUTDT6 (GPIO_BASE + 0x5408U) 118*54fd6939SJiyong Park #define GPIO_INTDT6 (GPIO_BASE + 0x5410U) 119*54fd6939SJiyong Park #define GPIO_INTCLR6 (GPIO_BASE + 0x5414U) 120*54fd6939SJiyong Park #define GPIO_INTMSK6 (GPIO_BASE + 0x5418U) 121*54fd6939SJiyong Park #define GPIO_MSKCLR6 (GPIO_BASE + 0x541CU) 122*54fd6939SJiyong Park #define GPIO_POSNEG6 (GPIO_BASE + 0x5420U) 123*54fd6939SJiyong Park #define GPIO_EDGLEVEL6 (GPIO_BASE + 0x5424U) 124*54fd6939SJiyong Park #define GPIO_FILONOFF6 (GPIO_BASE + 0x5428U) 125*54fd6939SJiyong Park #define GPIO_INTMSKS6 (GPIO_BASE + 0x5438U) 126*54fd6939SJiyong Park #define GPIO_MSKCLRS6 (GPIO_BASE + 0x543CU) 127*54fd6939SJiyong Park #define GPIO_OUTDTSEL6 (GPIO_BASE + 0x5440U) 128*54fd6939SJiyong Park #define GPIO_OUTDTH6 (GPIO_BASE + 0x5444U) 129*54fd6939SJiyong Park #define GPIO_OUTDTL6 (GPIO_BASE + 0x5448U) 130*54fd6939SJiyong Park #define GPIO_BOTHEDGE6 (GPIO_BASE + 0x544CU) 131*54fd6939SJiyong Park #define GPIO_IOINTSEL7 (GPIO_BASE + 0x5800U) 132*54fd6939SJiyong Park #define GPIO_INOUTSEL7 (GPIO_BASE + 0x5804U) 133*54fd6939SJiyong Park #define GPIO_OUTDT7 (GPIO_BASE + 0x5808U) 134*54fd6939SJiyong Park #define GPIO_INDT7 (GPIO_BASE + 0x580CU) 135*54fd6939SJiyong Park #define GPIO_INTDT7 (GPIO_BASE + 0x5810U) 136*54fd6939SJiyong Park #define GPIO_INTCLR7 (GPIO_BASE + 0x5814U) 137*54fd6939SJiyong Park #define GPIO_INTMSK7 (GPIO_BASE + 0x5818U) 138*54fd6939SJiyong Park #define GPIO_MSKCLR7 (GPIO_BASE + 0x581CU) 139*54fd6939SJiyong Park #define GPIO_POSNEG7 (GPIO_BASE + 0x5820U) 140*54fd6939SJiyong Park #define GPIO_EDGLEVEL7 (GPIO_BASE + 0x5824U) 141*54fd6939SJiyong Park #define GPIO_FILONOFF7 (GPIO_BASE + 0x5828U) 142*54fd6939SJiyong Park #define GPIO_INTMSKS7 (GPIO_BASE + 0x5838U) 143*54fd6939SJiyong Park #define GPIO_MSKCLRS7 (GPIO_BASE + 0x583CU) 144*54fd6939SJiyong Park #define GPIO_OUTDTSEL7 (GPIO_BASE + 0x5840U) 145*54fd6939SJiyong Park #define GPIO_OUTDTH7 (GPIO_BASE + 0x5844U) 146*54fd6939SJiyong Park #define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U) 147*54fd6939SJiyong Park #define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU) 148*54fd6939SJiyong Park 149*54fd6939SJiyong Park /* Pin functon base address */ 150*54fd6939SJiyong Park #define PFC_BASE (0xE6060000U) 151*54fd6939SJiyong Park 152*54fd6939SJiyong Park /* Pin functon registers */ 153*54fd6939SJiyong Park #define PFC_PMMR (PFC_BASE + 0x0000U) 154*54fd6939SJiyong Park #define PFC_GPSR0 (PFC_BASE + 0x0100U) 155*54fd6939SJiyong Park #define PFC_GPSR1 (PFC_BASE + 0x0104U) 156*54fd6939SJiyong Park #define PFC_GPSR2 (PFC_BASE + 0x0108U) 157*54fd6939SJiyong Park #define PFC_GPSR3 (PFC_BASE + 0x010CU) 158*54fd6939SJiyong Park #define PFC_GPSR4 (PFC_BASE + 0x0110U) 159*54fd6939SJiyong Park #define PFC_GPSR5 (PFC_BASE + 0x0114U) 160*54fd6939SJiyong Park #define PFC_GPSR6 (PFC_BASE + 0x0118U) 161*54fd6939SJiyong Park #define PFC_GPSR7 (PFC_BASE + 0x011CU) 162*54fd6939SJiyong Park #define PFC_IPSR0 (PFC_BASE + 0x0200U) 163*54fd6939SJiyong Park #define PFC_IPSR1 (PFC_BASE + 0x0204U) 164*54fd6939SJiyong Park #define PFC_IPSR2 (PFC_BASE + 0x0208U) 165*54fd6939SJiyong Park #define PFC_IPSR3 (PFC_BASE + 0x020CU) 166*54fd6939SJiyong Park #define PFC_IPSR4 (PFC_BASE + 0x0210U) 167*54fd6939SJiyong Park #define PFC_IPSR5 (PFC_BASE + 0x0214U) 168*54fd6939SJiyong Park #define PFC_IPSR6 (PFC_BASE + 0x0218U) 169*54fd6939SJiyong Park #define PFC_IPSR7 (PFC_BASE + 0x021CU) 170*54fd6939SJiyong Park #define PFC_IPSR8 (PFC_BASE + 0x0220U) 171*54fd6939SJiyong Park #define PFC_IPSR9 (PFC_BASE + 0x0224U) 172*54fd6939SJiyong Park #define PFC_IPSR10 (PFC_BASE + 0x0228U) 173*54fd6939SJiyong Park #define PFC_IPSR11 (PFC_BASE + 0x022CU) 174*54fd6939SJiyong Park #define PFC_IPSR12 (PFC_BASE + 0x0230U) 175*54fd6939SJiyong Park #define PFC_IPSR13 (PFC_BASE + 0x0234U) 176*54fd6939SJiyong Park #define PFC_IPSR14 (PFC_BASE + 0x0238U) 177*54fd6939SJiyong Park #define PFC_IPSR15 (PFC_BASE + 0x023CU) 178*54fd6939SJiyong Park #define PFC_IPSR16 (PFC_BASE + 0x0240U) 179*54fd6939SJiyong Park #define PFC_IPSR17 (PFC_BASE + 0x0244U) 180*54fd6939SJiyong Park #define PFC_IPSR18 (PFC_BASE + 0x0248U) 181*54fd6939SJiyong Park #define PFC_DRVCTRL0 (PFC_BASE + 0x0300U) 182*54fd6939SJiyong Park #define PFC_DRVCTRL1 (PFC_BASE + 0x0304U) 183*54fd6939SJiyong Park #define PFC_DRVCTRL2 (PFC_BASE + 0x0308U) 184*54fd6939SJiyong Park #define PFC_DRVCTRL3 (PFC_BASE + 0x030CU) 185*54fd6939SJiyong Park #define PFC_DRVCTRL4 (PFC_BASE + 0x0310U) 186*54fd6939SJiyong Park #define PFC_DRVCTRL5 (PFC_BASE + 0x0314U) 187*54fd6939SJiyong Park #define PFC_DRVCTRL6 (PFC_BASE + 0x0318U) 188*54fd6939SJiyong Park #define PFC_DRVCTRL7 (PFC_BASE + 0x031CU) 189*54fd6939SJiyong Park #define PFC_DRVCTRL8 (PFC_BASE + 0x0320U) 190*54fd6939SJiyong Park #define PFC_DRVCTRL9 (PFC_BASE + 0x0324U) 191*54fd6939SJiyong Park #define PFC_DRVCTRL10 (PFC_BASE + 0x0328U) 192*54fd6939SJiyong Park #define PFC_DRVCTRL11 (PFC_BASE + 0x032CU) 193*54fd6939SJiyong Park #define PFC_DRVCTRL12 (PFC_BASE + 0x0330U) 194*54fd6939SJiyong Park #define PFC_DRVCTRL13 (PFC_BASE + 0x0334U) 195*54fd6939SJiyong Park #define PFC_DRVCTRL14 (PFC_BASE + 0x0338U) 196*54fd6939SJiyong Park #define PFC_DRVCTRL15 (PFC_BASE + 0x033CU) 197*54fd6939SJiyong Park #define PFC_DRVCTRL16 (PFC_BASE + 0x0340U) 198*54fd6939SJiyong Park #define PFC_DRVCTRL17 (PFC_BASE + 0x0344U) 199*54fd6939SJiyong Park #define PFC_DRVCTRL18 (PFC_BASE + 0x0348U) 200*54fd6939SJiyong Park #define PFC_DRVCTRL19 (PFC_BASE + 0x034CU) 201*54fd6939SJiyong Park #define PFC_DRVCTRL20 (PFC_BASE + 0x0350U) 202*54fd6939SJiyong Park #define PFC_DRVCTRL21 (PFC_BASE + 0x0354U) 203*54fd6939SJiyong Park #define PFC_DRVCTRL22 (PFC_BASE + 0x0358U) 204*54fd6939SJiyong Park #define PFC_DRVCTRL23 (PFC_BASE + 0x035CU) 205*54fd6939SJiyong Park #define PFC_DRVCTRL24 (PFC_BASE + 0x0360U) 206*54fd6939SJiyong Park #define PFC_POCCTRL0 (PFC_BASE + 0x0380U) 207*54fd6939SJiyong Park #define PFC_IOCTRL31 (PFC_BASE + 0x0384U) 208*54fd6939SJiyong Park #define PFC_POCCTRL2 (PFC_BASE + 0x0388U) 209*54fd6939SJiyong Park #define PFC_TDSELCTRL0 (PFC_BASE + 0x03C0U) 210*54fd6939SJiyong Park #define PFC_IOCTRL (PFC_BASE + 0x03E0U) 211*54fd6939SJiyong Park #define PFC_TSREG (PFC_BASE + 0x03E4U) 212*54fd6939SJiyong Park #define PFC_PUEN0 (PFC_BASE + 0x0400U) 213*54fd6939SJiyong Park #define PFC_PUEN1 (PFC_BASE + 0x0404U) 214*54fd6939SJiyong Park #define PFC_PUEN2 (PFC_BASE + 0x0408U) 215*54fd6939SJiyong Park #define PFC_PUEN3 (PFC_BASE + 0x040CU) 216*54fd6939SJiyong Park #define PFC_PUEN4 (PFC_BASE + 0x0410U) 217*54fd6939SJiyong Park #define PFC_PUEN5 (PFC_BASE + 0x0414U) 218*54fd6939SJiyong Park #define PFC_PUEN6 (PFC_BASE + 0x0418U) 219*54fd6939SJiyong Park #define PFC_PUD0 (PFC_BASE + 0x0440U) 220*54fd6939SJiyong Park #define PFC_PUD1 (PFC_BASE + 0x0444U) 221*54fd6939SJiyong Park #define PFC_PUD2 (PFC_BASE + 0x0448U) 222*54fd6939SJiyong Park #define PFC_PUD3 (PFC_BASE + 0x044CU) 223*54fd6939SJiyong Park #define PFC_PUD4 (PFC_BASE + 0x0450U) 224*54fd6939SJiyong Park #define PFC_PUD5 (PFC_BASE + 0x0454U) 225*54fd6939SJiyong Park #define PFC_PUD6 (PFC_BASE + 0x0458U) 226*54fd6939SJiyong Park #define PFC_MOD_SEL0 (PFC_BASE + 0x0500U) 227*54fd6939SJiyong Park #define PFC_MOD_SEL1 (PFC_BASE + 0x0504U) 228*54fd6939SJiyong Park #define PFC_MOD_SEL2 (PFC_BASE + 0x0508U) 229*54fd6939SJiyong Park 230*54fd6939SJiyong Park #endif /* PFC_REGS_H */ 231