xref: /aosp_15_r20/external/arm-trusted-firmware/drivers/nxp/csu/csu.c (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park  * Copyright 2020 NXP
3*54fd6939SJiyong Park  *
4*54fd6939SJiyong Park  * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park  *
6*54fd6939SJiyong Park  */
7*54fd6939SJiyong Park 
8*54fd6939SJiyong Park #include <endian.h>
9*54fd6939SJiyong Park 
10*54fd6939SJiyong Park #include <common/debug.h>
11*54fd6939SJiyong Park #include <csu.h>
12*54fd6939SJiyong Park #include <lib/mmio.h>
13*54fd6939SJiyong Park 
enable_layerscape_ns_access(struct csu_ns_dev_st * csu_ns_dev,uint32_t num,uintptr_t nxp_csu_addr)14*54fd6939SJiyong Park void enable_layerscape_ns_access(struct csu_ns_dev_st *csu_ns_dev,
15*54fd6939SJiyong Park 				 uint32_t num, uintptr_t nxp_csu_addr)
16*54fd6939SJiyong Park {
17*54fd6939SJiyong Park 	uint32_t *base = (uint32_t *)nxp_csu_addr;
18*54fd6939SJiyong Park 	uint32_t *reg;
19*54fd6939SJiyong Park 	uint32_t val;
20*54fd6939SJiyong Park 	int i;
21*54fd6939SJiyong Park 
22*54fd6939SJiyong Park 	for (i = 0; i < num; i++) {
23*54fd6939SJiyong Park 		reg = base + csu_ns_dev[i].ind / 2U;
24*54fd6939SJiyong Park 		val = be32toh(mmio_read_32((uintptr_t)reg));
25*54fd6939SJiyong Park 		if (csu_ns_dev[i].ind % 2U == 0U) {
26*54fd6939SJiyong Park 			val &= 0x0000ffffU;
27*54fd6939SJiyong Park 			val |= csu_ns_dev[i].val << 16U;
28*54fd6939SJiyong Park 		} else {
29*54fd6939SJiyong Park 			val &= 0xffff0000U;
30*54fd6939SJiyong Park 			val |= csu_ns_dev[i].val;
31*54fd6939SJiyong Park 		}
32*54fd6939SJiyong Park 		mmio_write_32((uintptr_t)reg, htobe32(val));
33*54fd6939SJiyong Park 	}
34*54fd6939SJiyong Park }
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