xref: /aosp_15_r20/external/arm-trusted-firmware/drivers/marvell/ddr_phy_access.h (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park  * Copyright (C) 2021 Marvell International Ltd.
3*54fd6939SJiyong Park  *
4*54fd6939SJiyong Park  * SPDX-License-Identifier:     BSD-3-Clause
5*54fd6939SJiyong Park  * https://spdx.org/licenses
6*54fd6939SJiyong Park  */
7*54fd6939SJiyong Park 
8*54fd6939SJiyong Park #include <plat_marvell.h>
9*54fd6939SJiyong Park 
10*54fd6939SJiyong Park #define DEVICE_BASE		0xF0000000
11*54fd6939SJiyong Park #define DDR_PHY_OFFSET		0x1000000
12*54fd6939SJiyong Park #define DDR_PHY_BASE_ADDR	(DEVICE_BASE + DDR_PHY_OFFSET)
13*54fd6939SJiyong Park 
14*54fd6939SJiyong Park int mvebu_ddr_phy_write(uintptr_t offset, uint16_t data);
15*54fd6939SJiyong Park int mvebu_ddr_phy_read(uintptr_t offset, uint16_t *read);
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