1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (C) 2018 Marvell International Ltd. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park * https://spdx.org/licenses 6*54fd6939SJiyong Park */ 7*54fd6939SJiyong Park 8*54fd6939SJiyong Park /* Those are parameters for xfi mode, which need to be tune for each board type. 9*54fd6939SJiyong Park * For known DB boards the parameters was already calibrated and placed under 10*54fd6939SJiyong Park * the plat/marvell/armada/a8k/<board_type>/board/phy-porting-layer.h 11*54fd6939SJiyong Park */ 12*54fd6939SJiyong Park struct xfi_params { 13*54fd6939SJiyong Park uint8_t g1_ffe_res_sel; 14*54fd6939SJiyong Park uint8_t g1_ffe_cap_sel; 15*54fd6939SJiyong Park uint8_t align90; 16*54fd6939SJiyong Park uint8_t g1_dfe_res; 17*54fd6939SJiyong Park uint8_t g1_amp; 18*54fd6939SJiyong Park uint8_t g1_emph; 19*54fd6939SJiyong Park uint8_t g1_emph_en; 20*54fd6939SJiyong Park uint8_t g1_tx_amp_adj; 21*54fd6939SJiyong Park uint8_t g1_tx_emph_en; 22*54fd6939SJiyong Park uint8_t g1_tx_emph; 23*54fd6939SJiyong Park uint8_t g1_rx_selmuff; 24*54fd6939SJiyong Park uint8_t g1_rx_selmufi; 25*54fd6939SJiyong Park uint8_t g1_rx_selmupf; 26*54fd6939SJiyong Park uint8_t g1_rx_selmupi; 27*54fd6939SJiyong Park _Bool valid; 28*54fd6939SJiyong Park }; 29*54fd6939SJiyong Park 30*54fd6939SJiyong Park struct sata_params { 31*54fd6939SJiyong Park uint8_t g1_amp; 32*54fd6939SJiyong Park uint8_t g2_amp; 33*54fd6939SJiyong Park uint8_t g3_amp; 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park uint8_t g1_emph; 36*54fd6939SJiyong Park uint8_t g2_emph; 37*54fd6939SJiyong Park uint8_t g3_emph; 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park uint8_t g1_emph_en; 40*54fd6939SJiyong Park uint8_t g2_emph_en; 41*54fd6939SJiyong Park uint8_t g3_emph_en; 42*54fd6939SJiyong Park 43*54fd6939SJiyong Park uint8_t g1_tx_amp_adj; 44*54fd6939SJiyong Park uint8_t g2_tx_amp_adj; 45*54fd6939SJiyong Park uint8_t g3_tx_amp_adj; 46*54fd6939SJiyong Park 47*54fd6939SJiyong Park uint8_t g1_tx_emph_en; 48*54fd6939SJiyong Park uint8_t g2_tx_emph_en; 49*54fd6939SJiyong Park uint8_t g3_tx_emph_en; 50*54fd6939SJiyong Park 51*54fd6939SJiyong Park uint8_t g1_tx_emph; 52*54fd6939SJiyong Park uint8_t g2_tx_emph; 53*54fd6939SJiyong Park uint8_t g3_tx_emph; 54*54fd6939SJiyong Park 55*54fd6939SJiyong Park uint8_t g3_dfe_res; 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park uint8_t g3_ffe_res_sel; 58*54fd6939SJiyong Park 59*54fd6939SJiyong Park uint8_t g3_ffe_cap_sel; 60*54fd6939SJiyong Park 61*54fd6939SJiyong Park uint8_t align90; 62*54fd6939SJiyong Park 63*54fd6939SJiyong Park uint8_t g1_rx_selmuff; 64*54fd6939SJiyong Park uint8_t g2_rx_selmuff; 65*54fd6939SJiyong Park uint8_t g3_rx_selmuff; 66*54fd6939SJiyong Park 67*54fd6939SJiyong Park uint8_t g1_rx_selmufi; 68*54fd6939SJiyong Park uint8_t g2_rx_selmufi; 69*54fd6939SJiyong Park uint8_t g3_rx_selmufi; 70*54fd6939SJiyong Park 71*54fd6939SJiyong Park uint8_t g1_rx_selmupf; 72*54fd6939SJiyong Park uint8_t g2_rx_selmupf; 73*54fd6939SJiyong Park uint8_t g3_rx_selmupf; 74*54fd6939SJiyong Park 75*54fd6939SJiyong Park uint8_t g1_rx_selmupi; 76*54fd6939SJiyong Park uint8_t g2_rx_selmupi; 77*54fd6939SJiyong Park uint8_t g3_rx_selmupi; 78*54fd6939SJiyong Park 79*54fd6939SJiyong Park uint8_t polarity_invert; 80*54fd6939SJiyong Park 81*54fd6939SJiyong Park _Bool valid; 82*54fd6939SJiyong Park }; 83*54fd6939SJiyong Park 84*54fd6939SJiyong Park struct usb_params { 85*54fd6939SJiyong Park uint8_t polarity_invert; 86*54fd6939SJiyong Park }; 87*54fd6939SJiyong Park 88*54fd6939SJiyong Park int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base, 89*54fd6939SJiyong Park uint8_t comphy_index); 90*54fd6939SJiyong Park int mvebu_cp110_comphy_power_off(uint64_t comphy_base, 91*54fd6939SJiyong Park uint8_t comphy_index, uint64_t comphy_mode); 92*54fd6939SJiyong Park int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index, 93*54fd6939SJiyong Park uint64_t comphy_mode, 94*54fd6939SJiyong Park uint64_t comphy_train_base); 95*54fd6939SJiyong Park int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base, 96*54fd6939SJiyong Park uint8_t comphy_index); 97*54fd6939SJiyong Park int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index, 98*54fd6939SJiyong Park uint32_t comphy_mode, uint32_t command); 99*54fd6939SJiyong Park 100*54fd6939SJiyong Park #define COMPHY_POLARITY_NO_INVERT 0 101*54fd6939SJiyong Park #define COMPHY_POLARITY_TXD_INVERT 1 102*54fd6939SJiyong Park #define COMPHY_POLARITY_RXD_INVERT 2 103