1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2017 - 2020, Broadcom 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef IPROC_QSPI_H 8*54fd6939SJiyong Park #define IPROC_QSPI_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <platform_def.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /*SPI configuration enable*/ 13*54fd6939SJiyong Park #define IPROC_QSPI_CLK_SPEED 62500000 14*54fd6939SJiyong Park #define SPI_CPHA (1 << 0) 15*54fd6939SJiyong Park #define SPI_CPOL (1 << 1) 16*54fd6939SJiyong Park #define IPROC_QSPI_MODE0 0 17*54fd6939SJiyong Park #define IPROC_QSPI_MODE3 (SPI_CPOL|SPI_CPHA) 18*54fd6939SJiyong Park 19*54fd6939SJiyong Park #define IPROC_QSPI_BUS 0 20*54fd6939SJiyong Park #define IPROC_QSPI_CS 0 21*54fd6939SJiyong Park #define IPROC_QSPI_BASE_REG QSPI_CTRL_BASE_ADDR 22*54fd6939SJiyong Park #define IPROC_QSPI_CRU_CONTROL_REG QSPI_CLK_CTRL 23*54fd6939SJiyong Park 24*54fd6939SJiyong Park #define QSPI_AXI_CLK 200000000 25*54fd6939SJiyong Park 26*54fd6939SJiyong Park #define QSPI_RETRY_COUNT_US_MAX 200000 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park /* Chip attributes */ 29*54fd6939SJiyong Park #define QSPI_REG_BASE IPROC_QSPI_BASE_REG 30*54fd6939SJiyong Park #define CRU_CONTROL_REG IPROC_QSPI_CRU_CONTROL_REG 31*54fd6939SJiyong Park #define SPBR_DIV_MIN 8U 32*54fd6939SJiyong Park #define SPBR_DIV_MAX 255U 33*54fd6939SJiyong Park #define NUM_CDRAM_BYTES 16U 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park /* Register fields */ 36*54fd6939SJiyong Park #define MSPI_SPCR0_MSB_BITS_8 0x00000020 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park /* Flash opcode and parameters */ 39*54fd6939SJiyong Park #define CDRAM_PCS0 2 40*54fd6939SJiyong Park #define CDRAM_CONT (1 << 7) 41*54fd6939SJiyong Park #define CDRAM_BITS_EN (1 << 6) 42*54fd6939SJiyong Park #define CDRAM_QUAD_MODE (1 << 8) 43*54fd6939SJiyong Park #define CDRAM_RBIT_INPUT (1 << 10) 44*54fd6939SJiyong Park 45*54fd6939SJiyong Park /* MSPI registers */ 46*54fd6939SJiyong Park #define QSPI_MSPI_MODE_REG_BASE (QSPI_REG_BASE + 0x200) 47*54fd6939SJiyong Park #define MSPI_SPCR0_LSB_REG 0x000 48*54fd6939SJiyong Park #define MSPI_SPCR0_MSB_REG 0x004 49*54fd6939SJiyong Park #define MSPI_SPCR1_LSB_REG 0x008 50*54fd6939SJiyong Park #define MSPI_SPCR1_MSB_REG 0x00c 51*54fd6939SJiyong Park #define MSPI_NEWQP_REG 0x010 52*54fd6939SJiyong Park #define MSPI_ENDQP_REG 0x014 53*54fd6939SJiyong Park #define MSPI_SPCR2_REG 0x018 54*54fd6939SJiyong Park #define MSPI_STATUS_REG 0x020 55*54fd6939SJiyong Park #define MSPI_CPTQP_REG 0x024 56*54fd6939SJiyong Park #define MSPI_TXRAM_REG 0x040 57*54fd6939SJiyong Park #define MSPI_RXRAM_REG 0x0c0 58*54fd6939SJiyong Park #define MSPI_CDRAM_REG 0x140 59*54fd6939SJiyong Park #define MSPI_WRITE_LOCK_REG 0x180 60*54fd6939SJiyong Park #define MSPI_DISABLE_FLUSH_GEN_REG 0x184 61*54fd6939SJiyong Park 62*54fd6939SJiyong Park #define MSPI_SPCR0_MSB_REG_MSTR_SHIFT 7 63*54fd6939SJiyong Park #define MSPI_SPCR0_MSB_REG_16_BITS_PER_WD_SHIFT (0 << 2) 64*54fd6939SJiyong Park #define MSPI_SPCR0_MSB_REG_MODE_MASK 0x3 65*54fd6939SJiyong Park 66*54fd6939SJiyong Park /* BSPI registers */ 67*54fd6939SJiyong Park #define QSPI_BSPI_MODE_REG_BASE QSPI_REG_BASE 68*54fd6939SJiyong Park #define BSPI_MAST_N_BOOT_CTRL_REG 0x008 69*54fd6939SJiyong Park #define BSPI_BUSY_STATUS_REG 0x00c 70*54fd6939SJiyong Park 71*54fd6939SJiyong Park #define MSPI_CMD_COMPLETE_MASK 1 72*54fd6939SJiyong Park #define BSPI_BUSY_MASK 1 73*54fd6939SJiyong Park #define MSPI_CTRL_MASK 1 74*54fd6939SJiyong Park 75*54fd6939SJiyong Park #define MSPI_SPE (1 << 6) 76*54fd6939SJiyong Park #define MSPI_CONT_AFTER_CMD (1 << 7) 77*54fd6939SJiyong Park 78*54fd6939SJiyong Park /* State */ 79*54fd6939SJiyong Park enum bcm_qspi_state { 80*54fd6939SJiyong Park QSPI_STATE_DISABLED, 81*54fd6939SJiyong Park QSPI_STATE_MSPI, 82*54fd6939SJiyong Park QSPI_STATE_BSPI 83*54fd6939SJiyong Park }; 84*54fd6939SJiyong Park 85*54fd6939SJiyong Park /* QSPI private data */ 86*54fd6939SJiyong Park struct bcmspi_priv { 87*54fd6939SJiyong Park /* Specified SPI parameters */ 88*54fd6939SJiyong Park uint32_t max_hz; 89*54fd6939SJiyong Park uint32_t spi_mode; 90*54fd6939SJiyong Park 91*54fd6939SJiyong Park /* State */ 92*54fd6939SJiyong Park enum bcm_qspi_state state; 93*54fd6939SJiyong Park int mspi_16bit; 94*54fd6939SJiyong Park 95*54fd6939SJiyong Park /* Registers */ 96*54fd6939SJiyong Park uintptr_t mspi_hw; 97*54fd6939SJiyong Park uintptr_t bspi_hw; 98*54fd6939SJiyong Park }; 99*54fd6939SJiyong Park 100*54fd6939SJiyong Park int iproc_qspi_setup(uint32_t bus, uint32_t cs, 101*54fd6939SJiyong Park uint32_t max_hz, uint32_t mode); 102*54fd6939SJiyong Park int iproc_qspi_claim_bus(void); 103*54fd6939SJiyong Park void iproc_qspi_release_bus(void); 104*54fd6939SJiyong Park int iproc_qspi_xfer(uint32_t bitlen, const void *dout, 105*54fd6939SJiyong Park void *din, unsigned long flags); 106*54fd6939SJiyong Park 107*54fd6939SJiyong Park #endif /* _IPROC_QSPI_H_ */ 108