1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2019, Arm Limited. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #include <assert.h> 8*54fd6939SJiyong Park #include <drivers/arm/scu.h> 9*54fd6939SJiyong Park #include <lib/mmio.h> 10*54fd6939SJiyong Park #include <plat/common/platform.h> 11*54fd6939SJiyong Park #include <stdint.h> 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park /******************************************************************************* 14*54fd6939SJiyong Park * Turn ON snoop control unit. This is needed to synchronize the data between 15*54fd6939SJiyong Park * CPU's. 16*54fd6939SJiyong Park ******************************************************************************/ enable_snoop_ctrl_unit(uintptr_t base)17*54fd6939SJiyong Parkvoid enable_snoop_ctrl_unit(uintptr_t base) 18*54fd6939SJiyong Park { 19*54fd6939SJiyong Park uint32_t scu_ctrl; 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park INFO("[SCU]: enabling snoop control unit ... \n"); 22*54fd6939SJiyong Park 23*54fd6939SJiyong Park assert(base != 0U); 24*54fd6939SJiyong Park scu_ctrl = mmio_read_32(base + SCU_CTRL_REG); 25*54fd6939SJiyong Park 26*54fd6939SJiyong Park /* already enabled? */ 27*54fd6939SJiyong Park if ((scu_ctrl & SCU_ENABLE_BIT) != 0) { 28*54fd6939SJiyong Park return; 29*54fd6939SJiyong Park } 30*54fd6939SJiyong Park 31*54fd6939SJiyong Park scu_ctrl |= SCU_ENABLE_BIT; 32*54fd6939SJiyong Park mmio_write_32(base + SCU_CTRL_REG, scu_ctrl); 33*54fd6939SJiyong Park } 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park /******************************************************************************* 36*54fd6939SJiyong Park * Snoop Control Unit configuration register. This is read-only register and 37*54fd6939SJiyong Park * contains information such as 38*54fd6939SJiyong Park * - number of CPUs present 39*54fd6939SJiyong Park * - is a particular CPU operating in SMP mode or AMP mode 40*54fd6939SJiyong Park * - data cache size of a particular CPU 41*54fd6939SJiyong Park * - does SCU has ACP port 42*54fd6939SJiyong Park * - is L2CPRESENT 43*54fd6939SJiyong Park * NOTE: user of this API should interpert the bits in this register according 44*54fd6939SJiyong Park * to the TRM 45*54fd6939SJiyong Park ******************************************************************************/ read_snoop_ctrl_unit_cfg(uintptr_t base)46*54fd6939SJiyong Parkuint32_t read_snoop_ctrl_unit_cfg(uintptr_t base) 47*54fd6939SJiyong Park { 48*54fd6939SJiyong Park assert(base != 0U); 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park return mmio_read_32(base + SCU_CFG_REG); 51*54fd6939SJiyong Park } 52