1*54fd6939SJiyong ParkXilinx Zynq UltraScale+ MPSoC 2*54fd6939SJiyong Park============================= 3*54fd6939SJiyong Park 4*54fd6939SJiyong ParkTrusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq 5*54fd6939SJiyong ParkUltraScale + MPSoC. 6*54fd6939SJiyong ParkThe platform only uses the runtime part of TF-A as ZynqMP already has a 7*54fd6939SJiyong ParkBootROM (BL1) and FSBL (BL2). 8*54fd6939SJiyong Park 9*54fd6939SJiyong ParkBL31 is TF-A. 10*54fd6939SJiyong ParkBL32 is an optional Secure Payload. 11*54fd6939SJiyong ParkBL33 is the non-secure world software (U-Boot, Linux etc). 12*54fd6939SJiyong Park 13*54fd6939SJiyong ParkTo build: 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park.. code:: bash 16*54fd6939SJiyong Park 17*54fd6939SJiyong Park make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31 18*54fd6939SJiyong Park 19*54fd6939SJiyong ParkTo build bl32 TSP you have to rebuild bl31 too: 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park.. code:: bash 22*54fd6939SJiyong Park 23*54fd6939SJiyong Park make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32 24*54fd6939SJiyong Park 25*54fd6939SJiyong ParkTo build TF-A for JTAG DCC console: 26*54fd6939SJiyong Park 27*54fd6939SJiyong Park.. code:: bash 28*54fd6939SJiyong Park 29*54fd6939SJiyong Park make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc 30*54fd6939SJiyong Park 31*54fd6939SJiyong ParkZynqMP platform specific build options 32*54fd6939SJiyong Park-------------------------------------- 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary. 35*54fd6939SJiyong Park- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary. 36*54fd6939SJiyong Park- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary. 37*54fd6939SJiyong Park- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary. 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park- ``ZYNQMP_CONSOLE``: Select the console driver. Options: 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park - ``cadence``, ``cadence0``: Cadence UART 0 42*54fd6939SJiyong Park - ``cadence1`` : Cadence UART 1 43*54fd6939SJiyong Park 44*54fd6939SJiyong ParkFSBL->TF-A Parameter Passing 45*54fd6939SJiyong Park---------------------------- 46*54fd6939SJiyong Park 47*54fd6939SJiyong ParkThe FSBL populates a data structure with image information for TF-A. TF-A uses 48*54fd6939SJiyong Parkthat data to hand off to the loaded images. The address of the handoff data 49*54fd6939SJiyong Parkstructure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The 50*54fd6939SJiyong Parkregister is free to be used by other software once TF-A has brought up 51*54fd6939SJiyong Parkfurther firmware images. 52*54fd6939SJiyong Park 53*54fd6939SJiyong ParkPower Domain Tree 54*54fd6939SJiyong Park----------------- 55*54fd6939SJiyong Park 56*54fd6939SJiyong ParkThe following power domain tree represents the power domain model used by TF-A 57*54fd6939SJiyong Parkfor ZynqMP: 58*54fd6939SJiyong Park 59*54fd6939SJiyong Park:: 60*54fd6939SJiyong Park 61*54fd6939SJiyong Park +-+ 62*54fd6939SJiyong Park |0| 63*54fd6939SJiyong Park +-+ 64*54fd6939SJiyong Park +-------+---+---+-------+ 65*54fd6939SJiyong Park | | | | 66*54fd6939SJiyong Park | | | | 67*54fd6939SJiyong Park v v v v 68*54fd6939SJiyong Park +-+ +-+ +-+ +-+ 69*54fd6939SJiyong Park |0| |1| |2| |3| 70*54fd6939SJiyong Park +-+ +-+ +-+ +-+ 71*54fd6939SJiyong Park 72*54fd6939SJiyong ParkThe 4 leaf power domains represent the individual A53 cores, while resources 73*54fd6939SJiyong Parkcommon to the cluster are grouped in the power domain on the top. 74