1Porting Guide 2============= 3 4Introduction 5------------ 6 7Porting Trusted Firmware-A (TF-A) to a new platform involves making some 8mandatory and optional modifications for both the cold and warm boot paths. 9Modifications consist of: 10 11- Implementing a platform-specific function or variable, 12- Setting up the execution context in a certain way, or 13- Defining certain constants (for example #defines). 14 15The platform-specific functions and variables are declared in 16``include/plat/common/platform.h``. The firmware provides a default 17implementation of variables and functions to fulfill the optional requirements. 18These implementations are all weakly defined; they are provided to ease the 19porting effort. Each platform port can override them with its own implementation 20if the default implementation is inadequate. 21 22Some modifications are common to all Boot Loader (BL) stages. Section 2 23discusses these in detail. The subsequent sections discuss the remaining 24modifications for each BL stage in detail. 25 26Please refer to the :ref:`Platform Compatibility Policy` for the policy 27regarding compatibility and deprecation of these porting interfaces. 28 29Only Arm development platforms (such as FVP and Juno) may use the 30functions/definitions in ``include/plat/arm/common/`` and the corresponding 31source files in ``plat/arm/common/``. This is done so that there are no 32dependencies between platforms maintained by different people/companies. If you 33want to use any of the functionality present in ``plat/arm`` files, please 34create a pull request that moves the code to ``plat/common`` so that it can be 35discussed. 36 37Common modifications 38-------------------- 39 40This section covers the modifications that should be made by the platform for 41each BL stage to correctly port the firmware stack. They are categorized as 42either mandatory or optional. 43 44Common mandatory modifications 45------------------------------ 46 47A platform port must enable the Memory Management Unit (MMU) as well as the 48instruction and data caches for each BL stage. Setting up the translation 49tables is the responsibility of the platform port because memory maps differ 50across platforms. A memory translation library (see ``lib/xlat_tables/``) is 51provided to help in this setup. 52 53Note that although this library supports non-identity mappings, this is intended 54only for re-mapping peripheral physical addresses and allows platforms with high 55I/O addresses to reduce their virtual address space. All other addresses 56corresponding to code and data must currently use an identity mapping. 57 58Also, the only translation granule size supported in TF-A is 4KB, as various 59parts of the code assume that is the case. It is not possible to switch to 6016 KB or 64 KB granule sizes at the moment. 61 62In Arm standard platforms, each BL stage configures the MMU in the 63platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 64an identity mapping for all addresses. 65 66If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 67block of identity mapped secure memory with Device-nGnRE attributes aligned to 68page boundary (4K) for each BL stage. All sections which allocate coherent 69memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 70section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 71possible for the firmware to place variables in it using the following C code 72directive: 73 74:: 75 76 __section("bakery_lock") 77 78Or alternatively the following assembler code directive: 79 80:: 81 82 .section bakery_lock 83 84The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 85used to allocate any data structures that are accessed both when a CPU is 86executing with its MMU and caches enabled, and when it's running with its MMU 87and caches disabled. Examples are given below. 88 89The following variables, functions and constants must be defined by the platform 90for the firmware to work correctly. 91 92File : platform_def.h [mandatory] 93~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 94 95Each platform must ensure that a header file of this name is in the system 96include path with the following constants defined. This will require updating 97the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. 98 99Platform ports may optionally use the file ``include/plat/common/common_def.h``, 100which provides typical values for some of the constants below. These values are 101likely to be suitable for all platform ports. 102 103- **#define : PLATFORM_LINKER_FORMAT** 104 105 Defines the linker format used by the platform, for example 106 ``elf64-littleaarch64``. 107 108- **#define : PLATFORM_LINKER_ARCH** 109 110 Defines the processor architecture for the linker by the platform, for 111 example ``aarch64``. 112 113- **#define : PLATFORM_STACK_SIZE** 114 115 Defines the normal stack memory available to each CPU. This constant is used 116 by ``plat/common/aarch64/platform_mp_stack.S`` and 117 ``plat/common/aarch64/platform_up_stack.S``. 118 119- **#define : CACHE_WRITEBACK_GRANULE** 120 121 Defines the size in bits of the largest cache line across all the cache 122 levels in the platform. 123 124- **#define : FIRMWARE_WELCOME_STR** 125 126 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 127 function. 128 129- **#define : PLATFORM_CORE_COUNT** 130 131 Defines the total number of CPUs implemented by the platform across all 132 clusters in the system. 133 134- **#define : PLAT_NUM_PWR_DOMAINS** 135 136 Defines the total number of nodes in the power domain topology 137 tree at all the power domain levels used by the platform. 138 This macro is used by the PSCI implementation to allocate 139 data structures to represent power domain topology. 140 141- **#define : PLAT_MAX_PWR_LVL** 142 143 Defines the maximum power domain level that the power management operations 144 should apply to. More often, but not always, the power domain level 145 corresponds to affinity level. This macro allows the PSCI implementation 146 to know the highest power domain level that it should consider for power 147 management operations in the system that the platform implements. For 148 example, the Base AEM FVP implements two clusters with a configurable 149 number of CPUs and it reports the maximum power domain level as 1. 150 151- **#define : PLAT_MAX_OFF_STATE** 152 153 Defines the local power state corresponding to the deepest power down 154 possible at every power domain level in the platform. The local power 155 states for each level may be sparsely allocated between 0 and this value 156 with 0 being reserved for the RUN state. The PSCI implementation uses this 157 value to initialize the local power states of the power domain nodes and 158 to specify the requested power state for a PSCI_CPU_OFF call. 159 160- **#define : PLAT_MAX_RET_STATE** 161 162 Defines the local power state corresponding to the deepest retention state 163 possible at every power domain level in the platform. This macro should be 164 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the 165 PSCI implementation to distinguish between retention and power down local 166 power states within PSCI_CPU_SUSPEND call. 167 168- **#define : PLAT_MAX_PWR_LVL_STATES** 169 170 Defines the maximum number of local power states per power domain level 171 that the platform supports. The default value of this macro is 2 since 172 most platforms just support a maximum of two local power states at each 173 power domain level (power-down and retention). If the platform needs to 174 account for more local power states, then it must redefine this macro. 175 176 Currently, this macro is used by the Generic PSCI implementation to size 177 the array used for PSCI_STAT_COUNT/RESIDENCY accounting. 178 179- **#define : BL1_RO_BASE** 180 181 Defines the base address in secure ROM where BL1 originally lives. Must be 182 aligned on a page-size boundary. 183 184- **#define : BL1_RO_LIMIT** 185 186 Defines the maximum address in secure ROM that BL1's actual content (i.e. 187 excluding any data section allocated at runtime) can occupy. 188 189- **#define : BL1_RW_BASE** 190 191 Defines the base address in secure RAM where BL1's read-write data will live 192 at runtime. Must be aligned on a page-size boundary. 193 194- **#define : BL1_RW_LIMIT** 195 196 Defines the maximum address in secure RAM that BL1's read-write data can 197 occupy at runtime. 198 199- **#define : BL2_BASE** 200 201 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 202 Must be aligned on a page-size boundary. This constant is not applicable 203 when BL2_IN_XIP_MEM is set to '1'. 204 205- **#define : BL2_LIMIT** 206 207 Defines the maximum address in secure RAM that the BL2 image can occupy. 208 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 209 210- **#define : BL2_RO_BASE** 211 212 Defines the base address in secure XIP memory where BL2 RO section originally 213 lives. Must be aligned on a page-size boundary. This constant is only needed 214 when BL2_IN_XIP_MEM is set to '1'. 215 216- **#define : BL2_RO_LIMIT** 217 218 Defines the maximum address in secure XIP memory that BL2's actual content 219 (i.e. excluding any data section allocated at runtime) can occupy. This 220 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 221 222- **#define : BL2_RW_BASE** 223 224 Defines the base address in secure RAM where BL2's read-write data will live 225 at runtime. Must be aligned on a page-size boundary. This constant is only 226 needed when BL2_IN_XIP_MEM is set to '1'. 227 228- **#define : BL2_RW_LIMIT** 229 230 Defines the maximum address in secure RAM that BL2's read-write data can 231 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 232 to '1'. 233 234- **#define : BL31_BASE** 235 236 Defines the base address in secure RAM where BL2 loads the BL31 binary 237 image. Must be aligned on a page-size boundary. 238 239- **#define : BL31_LIMIT** 240 241 Defines the maximum address in secure RAM that the BL31 image can occupy. 242 243For every image, the platform must define individual identifiers that will be 244used by BL1 or BL2 to load the corresponding image into memory from non-volatile 245storage. For the sake of performance, integer numbers will be used as 246identifiers. The platform will use those identifiers to return the relevant 247information about the image to be loaded (file handler, load address, 248authentication information, etc.). The following image identifiers are 249mandatory: 250 251- **#define : BL2_IMAGE_ID** 252 253 BL2 image identifier, used by BL1 to load BL2. 254 255- **#define : BL31_IMAGE_ID** 256 257 BL31 image identifier, used by BL2 to load BL31. 258 259- **#define : BL33_IMAGE_ID** 260 261 BL33 image identifier, used by BL2 to load BL33. 262 263If Trusted Board Boot is enabled, the following certificate identifiers must 264also be defined: 265 266- **#define : TRUSTED_BOOT_FW_CERT_ID** 267 268 BL2 content certificate identifier, used by BL1 to load the BL2 content 269 certificate. 270 271- **#define : TRUSTED_KEY_CERT_ID** 272 273 Trusted key certificate identifier, used by BL2 to load the trusted key 274 certificate. 275 276- **#define : SOC_FW_KEY_CERT_ID** 277 278 BL31 key certificate identifier, used by BL2 to load the BL31 key 279 certificate. 280 281- **#define : SOC_FW_CONTENT_CERT_ID** 282 283 BL31 content certificate identifier, used by BL2 to load the BL31 content 284 certificate. 285 286- **#define : NON_TRUSTED_FW_KEY_CERT_ID** 287 288 BL33 key certificate identifier, used by BL2 to load the BL33 key 289 certificate. 290 291- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** 292 293 BL33 content certificate identifier, used by BL2 to load the BL33 content 294 certificate. 295 296- **#define : FWU_CERT_ID** 297 298 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the 299 FWU content certificate. 300 301- **#define : PLAT_CRYPTOCELL_BASE** 302 303 This defines the base address of Arm® TrustZone® CryptoCell and must be 304 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 305 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 306 set. 307 308If the AP Firmware Updater Configuration image, BL2U is used, the following 309must also be defined: 310 311- **#define : BL2U_BASE** 312 313 Defines the base address in secure memory where BL1 copies the BL2U binary 314 image. Must be aligned on a page-size boundary. 315 316- **#define : BL2U_LIMIT** 317 318 Defines the maximum address in secure memory that the BL2U image can occupy. 319 320- **#define : BL2U_IMAGE_ID** 321 322 BL2U image identifier, used by BL1 to fetch an image descriptor 323 corresponding to BL2U. 324 325If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following 326must also be defined: 327 328- **#define : SCP_BL2U_IMAGE_ID** 329 330 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor 331 corresponding to SCP_BL2U. 332 333 .. note:: 334 TF-A does not provide source code for this image. 335 336If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must 337also be defined: 338 339- **#define : NS_BL1U_BASE** 340 341 Defines the base address in non-secure ROM where NS_BL1U executes. 342 Must be aligned on a page-size boundary. 343 344 .. note:: 345 TF-A does not provide source code for this image. 346 347- **#define : NS_BL1U_IMAGE_ID** 348 349 NS_BL1U image identifier, used by BL1 to fetch an image descriptor 350 corresponding to NS_BL1U. 351 352If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also 353be defined: 354 355- **#define : NS_BL2U_BASE** 356 357 Defines the base address in non-secure memory where NS_BL2U executes. 358 Must be aligned on a page-size boundary. 359 360 .. note:: 361 TF-A does not provide source code for this image. 362 363- **#define : NS_BL2U_IMAGE_ID** 364 365 NS_BL2U image identifier, used by BL1 to fetch an image descriptor 366 corresponding to NS_BL2U. 367 368For the the Firmware update capability of TRUSTED BOARD BOOT, the following 369macros may also be defined: 370 371- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** 372 373 Total number of images that can be loaded simultaneously. If the platform 374 doesn't specify any value, it defaults to 10. 375 376If a SCP_BL2 image is supported by the platform, the following constants must 377also be defined: 378 379- **#define : SCP_BL2_IMAGE_ID** 380 381 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory 382 from platform storage before being transferred to the SCP. 383 384- **#define : SCP_FW_KEY_CERT_ID** 385 386 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key 387 certificate (mandatory when Trusted Board Boot is enabled). 388 389- **#define : SCP_FW_CONTENT_CERT_ID** 390 391 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 392 content certificate (mandatory when Trusted Board Boot is enabled). 393 394If a BL32 image is supported by the platform, the following constants must 395also be defined: 396 397- **#define : BL32_IMAGE_ID** 398 399 BL32 image identifier, used by BL2 to load BL32. 400 401- **#define : TRUSTED_OS_FW_KEY_CERT_ID** 402 403 BL32 key certificate identifier, used by BL2 to load the BL32 key 404 certificate (mandatory when Trusted Board Boot is enabled). 405 406- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** 407 408 BL32 content certificate identifier, used by BL2 to load the BL32 content 409 certificate (mandatory when Trusted Board Boot is enabled). 410 411- **#define : BL32_BASE** 412 413 Defines the base address in secure memory where BL2 loads the BL32 binary 414 image. Must be aligned on a page-size boundary. 415 416- **#define : BL32_LIMIT** 417 418 Defines the maximum address that the BL32 image can occupy. 419 420If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 421platform, the following constants must also be defined: 422 423- **#define : TSP_SEC_MEM_BASE** 424 425 Defines the base address of the secure memory used by the TSP image on the 426 platform. This must be at the same address or below ``BL32_BASE``. 427 428- **#define : TSP_SEC_MEM_SIZE** 429 430 Defines the size of the secure memory used by the BL32 image on the 431 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully 432 accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` 433 and ``BL32_LIMIT``. 434 435- **#define : TSP_IRQ_SEC_PHY_TIMER** 436 437 Defines the ID of the secure physical generic timer interrupt used by the 438 TSP's interrupt handling code. 439 440If the platform port uses the translation table library code, the following 441constants must also be defined: 442 443- **#define : PLAT_XLAT_TABLES_DYNAMIC** 444 445 Optional flag that can be set per-image to enable the dynamic allocation of 446 regions even when the MMU is enabled. If not defined, only static 447 functionality will be available, if defined and set to 1 it will also 448 include the dynamic functionality. 449 450- **#define : MAX_XLAT_TABLES** 451 452 Defines the maximum number of translation tables that are allocated by the 453 translation table library code. To minimize the amount of runtime memory 454 used, choose the smallest value needed to map the required virtual addresses 455 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 456 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 457 as well. 458 459- **#define : MAX_MMAP_REGIONS** 460 461 Defines the maximum number of regions that are allocated by the translation 462 table library code. A region consists of physical base address, virtual base 463 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 464 defined in the ``mmap_region_t`` structure. The platform defines the regions 465 that should be mapped. Then, the translation table library will create the 466 corresponding tables and descriptors at runtime. To minimize the amount of 467 runtime memory used, choose the smallest value needed to register the 468 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 469 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 470 the dynamic regions as well. 471 472- **#define : PLAT_VIRT_ADDR_SPACE_SIZE** 473 474 Defines the total size of the virtual address space in bytes. For example, 475 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 476 477- **#define : PLAT_PHY_ADDR_SPACE_SIZE** 478 479 Defines the total size of the physical address space in bytes. For example, 480 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 481 482If the platform port uses the IO storage framework, the following constants 483must also be defined: 484 485- **#define : MAX_IO_DEVICES** 486 487 Defines the maximum number of registered IO devices. Attempting to register 488 more devices than this value using ``io_register_device()`` will fail with 489 -ENOMEM. 490 491- **#define : MAX_IO_HANDLES** 492 493 Defines the maximum number of open IO handles. Attempting to open more IO 494 entities than this value using ``io_open()`` will fail with -ENOMEM. 495 496- **#define : MAX_IO_BLOCK_DEVICES** 497 498 Defines the maximum number of registered IO block devices. Attempting to 499 register more devices this value using ``io_dev_open()`` will fail 500 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. 501 With this macro, multiple block devices could be supported at the same 502 time. 503 504If the platform needs to allocate data within the per-cpu data framework in 505BL31, it should define the following macro. Currently this is only required if 506the platform decides not to use the coherent memory section by undefining the 507``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 508required memory within the the per-cpu data to minimize wastage. 509 510- **#define : PLAT_PCPU_DATA_SIZE** 511 512 Defines the memory (in bytes) to be reserved within the per-cpu data 513 structure for use by the platform layer. 514 515The following constants are optional. They should be defined when the platform 516memory layout implies some image overlaying like in Arm standard platforms. 517 518- **#define : BL31_PROGBITS_LIMIT** 519 520 Defines the maximum address in secure RAM that the BL31's progbits sections 521 can occupy. 522 523- **#define : TSP_PROGBITS_LIMIT** 524 525 Defines the maximum address that the TSP's progbits sections can occupy. 526 527If the platform port uses the PL061 GPIO driver, the following constant may 528optionally be defined: 529 530- **PLAT_PL061_MAX_GPIOS** 531 Maximum number of GPIOs required by the platform. This allows control how 532 much memory is allocated for PL061 GPIO controllers. The default value is 533 534 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) 535 536If the platform port uses the partition driver, the following constant may 537optionally be defined: 538 539- **PLAT_PARTITION_MAX_ENTRIES** 540 Maximum number of partition entries required by the platform. This allows 541 control how much memory is allocated for partition entries. The default 542 value is 128. 543 For example, define the build flag in ``platform.mk``: 544 PLAT_PARTITION_MAX_ENTRIES := 12 545 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) 546 547- **PLAT_PARTITION_BLOCK_SIZE** 548 The size of partition block. It could be either 512 bytes or 4096 bytes. 549 The default value is 512. 550 For example, define the build flag in ``platform.mk``: 551 PLAT_PARTITION_BLOCK_SIZE := 4096 552 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) 553 554The following constant is optional. It should be defined to override the default 555behaviour of the ``assert()`` function (for example, to save memory). 556 557- **PLAT_LOG_LEVEL_ASSERT** 558 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 559 ``assert()`` prints the name of the file, the line number and the asserted 560 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 561 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 562 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 563 defined, it defaults to ``LOG_LEVEL``. 564 565File : plat_macros.S [mandatory] 566~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 567 568Each platform must ensure a file of this name is in the system include path with 569the following macro defined. In the Arm development platforms, this file is 570found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 571 572- **Macro : plat_crash_print_regs** 573 574 This macro allows the crash reporting routine to print relevant platform 575 registers in case of an unhandled exception in BL31. This aids in debugging 576 and this macro can be defined to be empty in case register reporting is not 577 desired. 578 579 For instance, GIC or interconnect registers may be helpful for 580 troubleshooting. 581 582Handling Reset 583-------------- 584 585BL1 by default implements the reset vector where execution starts from a cold 586or warm boot. BL31 can be optionally set as a reset vector using the 587``RESET_TO_BL31`` make variable. 588 589For each CPU, the reset vector code is responsible for the following tasks: 590 591#. Distinguishing between a cold boot and a warm boot. 592 593#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 594 the CPU is placed in a platform-specific state until the primary CPU 595 performs the necessary steps to remove it from this state. 596 597#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 598 specific address in the BL31 image in the same processor mode as it was 599 when released from reset. 600 601The following functions need to be implemented by the platform port to enable 602reset vector code to perform the above tasks. 603 604Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] 605~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 606 607:: 608 609 Argument : void 610 Return : uintptr_t 611 612This function is called with the MMU and caches disabled 613(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 614distinguishing between a warm and cold reset for the current CPU using 615platform-specific means. If it's a warm reset, then it returns the warm 616reset entrypoint point provided to ``plat_setup_psci_ops()`` during 617BL31 initialization. If it's a cold reset then this function must return zero. 618 619This function does not follow the Procedure Call Standard used by the 620Application Binary Interface for the Arm 64-bit architecture. The caller should 621not assume that callee saved registers are preserved across a call to this 622function. 623 624This function fulfills requirement 1 and 3 listed above. 625 626Note that for platforms that support programming the reset address, it is 627expected that a CPU will start executing code directly at the right address, 628both on a cold and warm reset. In this case, there is no need to identify the 629type of reset nor to query the warm reset entrypoint. Therefore, implementing 630this function is not required on such platforms. 631 632Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 633~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 634 635:: 636 637 Argument : void 638 639This function is called with the MMU and data caches disabled. It is responsible 640for placing the executing secondary CPU in a platform-specific state until the 641primary CPU performs the necessary actions to bring it out of that state and 642allow entry into the OS. This function must not return. 643 644In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 645itself off. The primary CPU is responsible for powering up the secondary CPUs 646when normal world software requires them. When booting an EL3 payload instead, 647they stay powered on and are put in a holding pen until their mailbox gets 648populated. 649 650This function fulfills requirement 2 above. 651 652Note that for platforms that can't release secondary CPUs out of reset, only the 653primary CPU will execute the cold boot code. Therefore, implementing this 654function is not required on such platforms. 655 656Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 657~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 658 659:: 660 661 Argument : void 662 Return : unsigned int 663 664This function identifies whether the current CPU is the primary CPU or a 665secondary CPU. A return value of zero indicates that the CPU is not the 666primary CPU, while a non-zero return value indicates that the CPU is the 667primary CPU. 668 669Note that for platforms that can't release secondary CPUs out of reset, only the 670primary CPU will execute the cold boot code. Therefore, there is no need to 671distinguish between primary and secondary CPUs and implementing this function is 672not required. 673 674Function : platform_mem_init() [mandatory] 675~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 676 677:: 678 679 Argument : void 680 Return : void 681 682This function is called before any access to data is made by the firmware, in 683order to carry out any essential memory initialization. 684 685Function: plat_get_rotpk_info() 686~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 687 688:: 689 690 Argument : void *, void **, unsigned int *, unsigned int * 691 Return : int 692 693This function is mandatory when Trusted Board Boot is enabled. It returns a 694pointer to the ROTPK stored in the platform (or a hash of it) and its length. 695The ROTPK must be encoded in DER format according to the following ASN.1 696structure: 697 698:: 699 700 AlgorithmIdentifier ::= SEQUENCE { 701 algorithm OBJECT IDENTIFIER, 702 parameters ANY DEFINED BY algorithm OPTIONAL 703 } 704 705 SubjectPublicKeyInfo ::= SEQUENCE { 706 algorithm AlgorithmIdentifier, 707 subjectPublicKey BIT STRING 708 } 709 710In case the function returns a hash of the key: 711 712:: 713 714 DigestInfo ::= SEQUENCE { 715 digestAlgorithm AlgorithmIdentifier, 716 digest OCTET STRING 717 } 718 719The function returns 0 on success. Any other value is treated as error by the 720Trusted Board Boot. The function also reports extra information related 721to the ROTPK in the flags parameter: 722 723:: 724 725 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 726 hash. 727 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 728 verification while the platform ROTPK is not deployed. 729 When this flag is set, the function does not need to 730 return a platform ROTPK, and the authentication 731 framework uses the ROTPK in the certificate without 732 verifying it against the platform value. This flag 733 must not be used in a deployed production environment. 734 735Function: plat_get_nv_ctr() 736~~~~~~~~~~~~~~~~~~~~~~~~~~~ 737 738:: 739 740 Argument : void *, unsigned int * 741 Return : int 742 743This function is mandatory when Trusted Board Boot is enabled. It returns the 744non-volatile counter value stored in the platform in the second argument. The 745cookie in the first argument may be used to select the counter in case the 746platform provides more than one (for example, on platforms that use the default 747TBBR CoT, the cookie will correspond to the OID values defined in 748TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). 749 750The function returns 0 on success. Any other value means the counter value could 751not be retrieved from the platform. 752 753Function: plat_set_nv_ctr() 754~~~~~~~~~~~~~~~~~~~~~~~~~~~ 755 756:: 757 758 Argument : void *, unsigned int 759 Return : int 760 761This function is mandatory when Trusted Board Boot is enabled. It sets a new 762counter value in the platform. The cookie in the first argument may be used to 763select the counter (as explained in plat_get_nv_ctr()). The second argument is 764the updated counter value to be written to the NV counter. 765 766The function returns 0 on success. Any other value means the counter value could 767not be updated. 768 769Function: plat_set_nv_ctr2() 770~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 771 772:: 773 774 Argument : void *, const auth_img_desc_t *, unsigned int 775 Return : int 776 777This function is optional when Trusted Board Boot is enabled. If this 778interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 779first argument passed is a cookie and is typically used to 780differentiate between a Non Trusted NV Counter and a Trusted NV 781Counter. The second argument is a pointer to an authentication image 782descriptor and may be used to decide if the counter is allowed to be 783updated or not. The third argument is the updated counter value to 784be written to the NV counter. 785 786The function returns 0 on success. Any other value means the counter value 787either could not be updated or the authentication image descriptor indicates 788that it is not allowed to be updated. 789 790Common mandatory function modifications 791--------------------------------------- 792 793The following functions are mandatory functions which need to be implemented 794by the platform port. 795 796Function : plat_my_core_pos() 797~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 798 799:: 800 801 Argument : void 802 Return : unsigned int 803 804This function returns the index of the calling CPU which is used as a 805CPU-specific linear index into blocks of memory (for example while allocating 806per-CPU stacks). This function will be invoked very early in the 807initialization sequence which mandates that this function should be 808implemented in assembly and should not rely on the availability of a C 809runtime environment. This function can clobber x0 - x8 and must preserve 810x9 - x29. 811 812This function plays a crucial role in the power domain topology framework in 813PSCI and details of this can be found in 814:ref:`PSCI Power Domain Tree Structure`. 815 816Function : plat_core_pos_by_mpidr() 817~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 818 819:: 820 821 Argument : u_register_t 822 Return : int 823 824This function validates the ``MPIDR`` of a CPU and converts it to an index, 825which can be used as a CPU-specific linear index into blocks of memory. In 826case the ``MPIDR`` is invalid, this function returns -1. This function will only 827be invoked by BL31 after the power domain topology is initialized and can 828utilize the C runtime environment. For further details about how TF-A 829represents the power domain topology and how this relates to the linear CPU 830index, please refer :ref:`PSCI Power Domain Tree Structure`. 831 832Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] 833~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 834 835:: 836 837 Arguments : void **heap_addr, size_t *heap_size 838 Return : int 839 840This function is invoked during Mbed TLS library initialisation to get a heap, 841by means of a starting address and a size. This heap will then be used 842internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS 843must be able to provide a heap to it. 844 845A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in 846which a heap is statically reserved during compile time inside every image 847(i.e. every BL stage) that utilises Mbed TLS. In this default implementation, 848the function simply returns the address and size of this "pre-allocated" heap. 849For a platform to use this default implementation, only a call to the helper 850from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. 851 852However, by writting their own implementation, platforms have the potential to 853optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is 854shared between BL1 and BL2 stages and, thus, the necessary space is not reserved 855twice. 856 857On success the function should return 0 and a negative error code otherwise. 858 859Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1] 860~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 861 862:: 863 864 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key, 865 size_t *key_len, unsigned int *flags, const uint8_t *img_id, 866 size_t img_id_len 867 Return : int 868 869This function provides a symmetric key (either SSK or BSSK depending on 870fw_enc_status) which is invoked during runtime decryption of encrypted 871firmware images. `plat/common/plat_bl_common.c` provides a dummy weak 872implementation for testing purposes which must be overridden by the platform 873trying to implement a real world firmware encryption use-case. 874 875It also allows the platform to pass symmetric key identifier rather than 876actual symmetric key which is useful in cases where the crypto backend provides 877secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER`` 878flag must be set in ``flags``. 879 880In addition to above a platform may also choose to provide an image specific 881symmetric key/identifier using img_id. 882 883On success the function should return 0 and a negative error code otherwise. 884 885Note that this API depends on ``DECRYPTION_SUPPORT`` build flag. 886 887Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1] 888~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 889 890:: 891 892 Argument : struct fwu_metadata *metadata 893 Return : void 894 895This function is mandatory when PSA_FWU_SUPPORT is enabled. 896It provides a means to retrieve image specification (offset in 897non-volatile storage and length) of active/updated images using the passed 898FWU metadata, and update I/O policies of active/updated images using retrieved 899image specification information. 900Further I/O layer operations such as I/O open, I/O read, etc. on these 901images rely on this function call. 902 903In Arm platforms, this function is used to set an I/O policy of the FIP image, 904container of all active/updated secure and non-secure images. 905 906Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1] 907~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 908 909:: 910 911 Argument : unsigned int image_id, uintptr_t *dev_handle, 912 uintptr_t *image_spec 913 Return : int 914 915This function is mandatory when PSA_FWU_SUPPORT is enabled. It is 916responsible for setting up the platform I/O policy of the requested metadata 917image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will 918be used to load this image from the platform's non-volatile storage. 919 920FWU metadata can not be always stored as a raw image in non-volatile storage 921to define its image specification (offset in non-volatile storage and length) 922statically in I/O policy. 923For example, the FWU metadata image is stored as a partition inside the GUID 924partition table image. Its specification is defined in the partition table 925that needs to be parsed dynamically. 926This function provides a means to retrieve such dynamic information to set 927the I/O policy of the FWU metadata image. 928Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata 929image relies on this function call. 930 931It returns '0' on success, otherwise a negative error value on error. 932Alongside, returns device handle and image specification from the I/O policy 933of the requested FWU metadata image. 934 935Common optional modifications 936----------------------------- 937 938The following are helper functions implemented by the firmware that perform 939common platform-specific tasks. A platform may choose to override these 940definitions. 941 942Function : plat_set_my_stack() 943~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 944 945:: 946 947 Argument : void 948 Return : void 949 950This function sets the current stack pointer to the normal memory stack that 951has been allocated for the current CPU. For BL images that only require a 952stack for the primary CPU, the UP version of the function is used. The size 953of the stack allocated to each CPU is specified by the platform defined 954constant ``PLATFORM_STACK_SIZE``. 955 956Common implementations of this function for the UP and MP BL images are 957provided in ``plat/common/aarch64/platform_up_stack.S`` and 958``plat/common/aarch64/platform_mp_stack.S`` 959 960Function : plat_get_my_stack() 961~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 962 963:: 964 965 Argument : void 966 Return : uintptr_t 967 968This function returns the base address of the normal memory stack that 969has been allocated for the current CPU. For BL images that only require a 970stack for the primary CPU, the UP version of the function is used. The size 971of the stack allocated to each CPU is specified by the platform defined 972constant ``PLATFORM_STACK_SIZE``. 973 974Common implementations of this function for the UP and MP BL images are 975provided in ``plat/common/aarch64/platform_up_stack.S`` and 976``plat/common/aarch64/platform_mp_stack.S`` 977 978Function : plat_report_exception() 979~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 980 981:: 982 983 Argument : unsigned int 984 Return : void 985 986A platform may need to report various information about its status when an 987exception is taken, for example the current exception level, the CPU security 988state (secure/non-secure), the exception type, and so on. This function is 989called in the following circumstances: 990 991- In BL1, whenever an exception is taken. 992- In BL2, whenever an exception is taken. 993 994The default implementation doesn't do anything, to avoid making assumptions 995about the way the platform displays its status information. 996 997For AArch64, this function receives the exception type as its argument. 998Possible values for exceptions types are listed in the 999``include/common/bl_common.h`` header file. Note that these constants are not 1000related to any architectural exception code; they are just a TF-A convention. 1001 1002For AArch32, this function receives the exception mode as its argument. 1003Possible values for exception modes are listed in the 1004``include/lib/aarch32/arch.h`` header file. 1005 1006Function : plat_reset_handler() 1007~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1008 1009:: 1010 1011 Argument : void 1012 Return : void 1013 1014A platform may need to do additional initialization after reset. This function 1015allows the platform to do the platform specific initializations. Platform 1016specific errata workarounds could also be implemented here. The API should 1017preserve the values of callee saved registers x19 to x29. 1018 1019The default implementation doesn't do anything. If a platform needs to override 1020the default implementation, refer to the :ref:`Firmware Design` for general 1021guidelines. 1022 1023Function : plat_disable_acp() 1024~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1025 1026:: 1027 1028 Argument : void 1029 Return : void 1030 1031This API allows a platform to disable the Accelerator Coherency Port (if 1032present) during a cluster power down sequence. The default weak implementation 1033doesn't do anything. Since this API is called during the power down sequence, 1034it has restrictions for stack usage and it can use the registers x0 - x17 as 1035scratch registers. It should preserve the value in x18 register as it is used 1036by the caller to store the return address. 1037 1038Function : plat_error_handler() 1039~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1040 1041:: 1042 1043 Argument : int 1044 Return : void 1045 1046This API is called when the generic code encounters an error situation from 1047which it cannot continue. It allows the platform to perform error reporting or 1048recovery actions (for example, reset the system). This function must not return. 1049 1050The parameter indicates the type of error using standard codes from ``errno.h``. 1051Possible errors reported by the generic code are: 1052 1053- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 1054 Board Boot is enabled) 1055- ``-ENOENT``: the requested image or certificate could not be found or an IO 1056 error was detected 1057- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 1058 error is usually an indication of an incorrect array size 1059 1060The default implementation simply spins. 1061 1062Function : plat_panic_handler() 1063~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1064 1065:: 1066 1067 Argument : void 1068 Return : void 1069 1070This API is called when the generic code encounters an unexpected error 1071situation from which it cannot recover. This function must not return, 1072and must be implemented in assembly because it may be called before the C 1073environment is initialized. 1074 1075.. note:: 1076 The address from where it was called is stored in x30 (Link Register). 1077 The default implementation simply spins. 1078 1079Function : plat_get_bl_image_load_info() 1080~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1081 1082:: 1083 1084 Argument : void 1085 Return : bl_load_info_t * 1086 1087This function returns pointer to the list of images that the platform has 1088populated to load. This function is invoked in BL2 to load the 1089BL3xx images. 1090 1091Function : plat_get_next_bl_params() 1092~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1093 1094:: 1095 1096 Argument : void 1097 Return : bl_params_t * 1098 1099This function returns a pointer to the shared memory that the platform has 1100kept aside to pass TF-A related information that next BL image needs. This 1101function is invoked in BL2 to pass this information to the next BL 1102image. 1103 1104Function : plat_get_stack_protector_canary() 1105~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1106 1107:: 1108 1109 Argument : void 1110 Return : u_register_t 1111 1112This function returns a random value that is used to initialize the canary used 1113when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable 1114value will weaken the protection as the attacker could easily write the right 1115value as part of the attack most of the time. Therefore, it should return a 1116true random number. 1117 1118.. warning:: 1119 For the protection to be effective, the global data need to be placed at 1120 a lower address than the stack bases. Failure to do so would allow an 1121 attacker to overwrite the canary as part of the stack buffer overflow attack. 1122 1123Function : plat_flush_next_bl_params() 1124~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1125 1126:: 1127 1128 Argument : void 1129 Return : void 1130 1131This function flushes to main memory all the image params that are passed to 1132next image. This function is invoked in BL2 to flush this information 1133to the next BL image. 1134 1135Function : plat_log_get_prefix() 1136~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1137 1138:: 1139 1140 Argument : unsigned int 1141 Return : const char * 1142 1143This function defines the prefix string corresponding to the `log_level` to be 1144prepended to all the log output from TF-A. The `log_level` (argument) will 1145correspond to one of the standard log levels defined in debug.h. The platform 1146can override the common implementation to define a different prefix string for 1147the log output. The implementation should be robust to future changes that 1148increase the number of log levels. 1149 1150Function : plat_get_soc_version() 1151~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1152 1153:: 1154 1155 Argument : void 1156 Return : int32_t 1157 1158This function returns soc version which mainly consist of below fields 1159 1160:: 1161 1162 soc_version[30:24] = JEP-106 continuation code for the SiP 1163 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP 1164 soc_version[15:0] = Implementation defined SoC ID 1165 1166Function : plat_get_soc_revision() 1167~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1168 1169:: 1170 1171 Argument : void 1172 Return : int32_t 1173 1174This function returns soc revision in below format 1175 1176:: 1177 1178 soc_revision[0:30] = SOC revision of specific SOC 1179 1180Function : plat_is_smccc_feature_available() 1181~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1182 1183:: 1184 1185 Argument : u_register_t 1186 Return : int32_t 1187 1188This function returns SMC_ARCH_CALL_SUCCESS if the platform supports 1189the SMCCC function specified in the argument; otherwise returns 1190SMC_ARCH_CALL_NOT_SUPPORTED. 1191 1192Function : plat_mboot_measure_image() 1193~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1194 1195:: 1196 1197 Argument : unsigned int, image_info_t * 1198 Return : void 1199 1200When the MEASURED_BOOT flag is enabled: 1201 1202- This function measures the given image and records its measurement using 1203 the measured boot backend driver. 1204- On the Arm FVP port, this function measures the given image using its 1205 passed id and information and then records that measurement in the 1206 Event Log buffer. 1207- This function must return 0 on success, a negative error code otherwise. 1208 1209When the MEASURED_BOOT flag is disabled, this function doesn't do anything. 1210 1211Modifications specific to a Boot Loader stage 1212--------------------------------------------- 1213 1214Boot Loader Stage 1 (BL1) 1215------------------------- 1216 1217BL1 implements the reset vector where execution starts from after a cold or 1218warm boot. For each CPU, BL1 is responsible for the following tasks: 1219 1220#. Handling the reset as described in section 2.2 1221 1222#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1223 only this CPU executes the remaining BL1 code, including loading and passing 1224 control to the BL2 stage. 1225 1226#. Identifying and starting the Firmware Update process (if required). 1227 1228#. Loading the BL2 image from non-volatile storage into secure memory at the 1229 address specified by the platform defined constant ``BL2_BASE``. 1230 1231#. Populating a ``meminfo`` structure with the following information in memory, 1232 accessible by BL2 immediately upon entry. 1233 1234 :: 1235 1236 meminfo.total_base = Base address of secure RAM visible to BL2 1237 meminfo.total_size = Size of secure RAM visible to BL2 1238 1239 By default, BL1 places this ``meminfo`` structure at the end of secure 1240 memory visible to BL2. 1241 1242 It is possible for the platform to decide where it wants to place the 1243 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1244 BL2 by overriding the weak default implementation of 1245 ``bl1_plat_handle_post_image_load`` API. 1246 1247The following functions need to be implemented by the platform port to enable 1248BL1 to perform the above tasks. 1249 1250Function : bl1_early_platform_setup() [mandatory] 1251~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1252 1253:: 1254 1255 Argument : void 1256 Return : void 1257 1258This function executes with the MMU and data caches disabled. It is only called 1259by the primary CPU. 1260 1261On Arm standard platforms, this function: 1262 1263- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1264 1265- Initializes a UART (PL011 console), which enables access to the ``printf`` 1266 family of functions in BL1. 1267 1268- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1269 the CCI slave interface corresponding to the cluster that includes the 1270 primary CPU. 1271 1272Function : bl1_plat_arch_setup() [mandatory] 1273~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1274 1275:: 1276 1277 Argument : void 1278 Return : void 1279 1280This function performs any platform-specific and architectural setup that the 1281platform requires. Platform-specific setup might include configuration of 1282memory controllers and the interconnect. 1283 1284In Arm standard platforms, this function enables the MMU. 1285 1286This function helps fulfill requirement 2 above. 1287 1288Function : bl1_platform_setup() [mandatory] 1289~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1290 1291:: 1292 1293 Argument : void 1294 Return : void 1295 1296This function executes with the MMU and data caches enabled. It is responsible 1297for performing any remaining platform-specific setup that can occur after the 1298MMU and data cache have been enabled. 1299 1300if support for multiple boot sources is required, it initializes the boot 1301sequence used by plat_try_next_boot_source(). 1302 1303In Arm standard platforms, this function initializes the storage abstraction 1304layer used to load the next bootloader image. 1305 1306This function helps fulfill requirement 4 above. 1307 1308Function : bl1_plat_sec_mem_layout() [mandatory] 1309~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1310 1311:: 1312 1313 Argument : void 1314 Return : meminfo * 1315 1316This function should only be called on the cold boot path. It executes with the 1317MMU and data caches enabled. The pointer returned by this function must point to 1318a ``meminfo`` structure containing the extents and availability of secure RAM for 1319the BL1 stage. 1320 1321:: 1322 1323 meminfo.total_base = Base address of secure RAM visible to BL1 1324 meminfo.total_size = Size of secure RAM visible to BL1 1325 1326This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1327populates a similar structure to tell BL2 the extents of memory available for 1328its own use. 1329 1330This function helps fulfill requirements 4 and 5 above. 1331 1332Function : bl1_plat_prepare_exit() [optional] 1333~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1334 1335:: 1336 1337 Argument : entry_point_info_t * 1338 Return : void 1339 1340This function is called prior to exiting BL1 in response to the 1341``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1342platform specific clean up or bookkeeping operations before transferring 1343control to the next image. It receives the address of the ``entry_point_info_t`` 1344structure passed from BL2. This function runs with MMU disabled. 1345 1346Function : bl1_plat_set_ep_info() [optional] 1347~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1348 1349:: 1350 1351 Argument : unsigned int image_id, entry_point_info_t *ep_info 1352 Return : void 1353 1354This function allows platforms to override ``ep_info`` for the given ``image_id``. 1355 1356The default implementation just returns. 1357 1358Function : bl1_plat_get_next_image_id() [optional] 1359~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1360 1361:: 1362 1363 Argument : void 1364 Return : unsigned int 1365 1366This and the following function must be overridden to enable the FWU feature. 1367 1368BL1 calls this function after platform setup to identify the next image to be 1369loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1370with the normal boot sequence, which loads and executes BL2. If the platform 1371returns a different image id, BL1 assumes that Firmware Update is required. 1372 1373The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1374platforms override this function to detect if firmware update is required, and 1375if so, return the first image in the firmware update process. 1376 1377Function : bl1_plat_get_image_desc() [optional] 1378~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1379 1380:: 1381 1382 Argument : unsigned int image_id 1383 Return : image_desc_t * 1384 1385BL1 calls this function to get the image descriptor information ``image_desc_t`` 1386for the provided ``image_id`` from the platform. 1387 1388The default implementation always returns a common BL2 image descriptor. Arm 1389standard platforms return an image descriptor corresponding to BL2 or one of 1390the firmware update images defined in the Trusted Board Boot Requirements 1391specification. 1392 1393Function : bl1_plat_handle_pre_image_load() [optional] 1394~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1395 1396:: 1397 1398 Argument : unsigned int image_id 1399 Return : int 1400 1401This function can be used by the platforms to update/use image information 1402corresponding to ``image_id``. This function is invoked in BL1, both in cold 1403boot and FWU code path, before loading the image. 1404 1405Function : bl1_plat_handle_post_image_load() [optional] 1406~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1407 1408:: 1409 1410 Argument : unsigned int image_id 1411 Return : int 1412 1413This function can be used by the platforms to update/use image information 1414corresponding to ``image_id``. This function is invoked in BL1, both in cold 1415boot and FWU code path, after loading and authenticating the image. 1416 1417The default weak implementation of this function calculates the amount of 1418Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1419structure at the beginning of this free memory and populates it. The address 1420of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1421information to BL2. 1422 1423Function : bl1_plat_fwu_done() [optional] 1424~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1425 1426:: 1427 1428 Argument : unsigned int image_id, uintptr_t image_src, 1429 unsigned int image_size 1430 Return : void 1431 1432BL1 calls this function when the FWU process is complete. It must not return. 1433The platform may override this function to take platform specific action, for 1434example to initiate the normal boot flow. 1435 1436The default implementation spins forever. 1437 1438Function : bl1_plat_mem_check() [mandatory] 1439~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1440 1441:: 1442 1443 Argument : uintptr_t mem_base, unsigned int mem_size, 1444 unsigned int flags 1445 Return : int 1446 1447BL1 calls this function while handling FWU related SMCs, more specifically when 1448copying or authenticating an image. Its responsibility is to ensure that the 1449region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1450that this memory corresponds to either a secure or non-secure memory region as 1451indicated by the security state of the ``flags`` argument. 1452 1453This function can safely assume that the value resulting from the addition of 1454``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1455overflow. 1456 1457This function must return 0 on success, a non-null error code otherwise. 1458 1459The default implementation of this function asserts therefore platforms must 1460override it when using the FWU feature. 1461 1462Function : bl1_plat_mboot_init() [optional] 1463~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1464 1465:: 1466 1467 Argument : void 1468 Return : void 1469 1470When the MEASURED_BOOT flag is enabled: 1471 1472- This function is used to initialize the backend driver(s) of measured boot. 1473- On the Arm FVP port, this function is used to initialize the Event Log 1474 backend driver, and also to write header information in the Event Log buffer. 1475 1476When the MEASURED_BOOT flag is disabled, this function doesn't do anything. 1477 1478Function : bl1_plat_mboot_finish() [optional] 1479~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1480 1481:: 1482 1483 Argument : void 1484 Return : void 1485 1486When the MEASURED_BOOT flag is enabled: 1487 1488- This function is used to finalize the measured boot backend driver(s), 1489 and also, set the information for the next bootloader component to 1490 extend the measurement if needed. 1491- On the Arm FVP port, this function is used to pass the base address of 1492 the Event Log buffer and its size to BL2 via tb_fw_config to extend the 1493 Event Log buffer with the measurement of various images loaded by BL2. 1494 It results in panic on error. 1495 1496When the MEASURED_BOOT flag is disabled, this function doesn't do anything. 1497 1498Boot Loader Stage 2 (BL2) 1499------------------------- 1500 1501The BL2 stage is executed only by the primary CPU, which is determined in BL1 1502using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1503``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1504``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1505non-volatile storage to secure/non-secure RAM. After all the images are loaded 1506then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1507images to be passed to the next BL image. 1508 1509The following functions must be implemented by the platform port to enable BL2 1510to perform the above tasks. 1511 1512Function : bl2_early_platform_setup2() [mandatory] 1513~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1514 1515:: 1516 1517 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1518 Return : void 1519 1520This function executes with the MMU and data caches disabled. It is only called 1521by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1522are platform specific. 1523 1524On Arm standard platforms, the arguments received are : 1525 1526 arg0 - Points to load address of FW_CONFIG 1527 1528 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1529 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1530 1531On Arm standard platforms, this function also: 1532 1533- Initializes a UART (PL011 console), which enables access to the ``printf`` 1534 family of functions in BL2. 1535 1536- Initializes the storage abstraction layer used to load further bootloader 1537 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1538 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1539 1540Function : bl2_plat_arch_setup() [mandatory] 1541~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1542 1543:: 1544 1545 Argument : void 1546 Return : void 1547 1548This function executes with the MMU and data caches disabled. It is only called 1549by the primary CPU. 1550 1551The purpose of this function is to perform any architectural initialization 1552that varies across platforms. 1553 1554On Arm standard platforms, this function enables the MMU. 1555 1556Function : bl2_platform_setup() [mandatory] 1557~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1558 1559:: 1560 1561 Argument : void 1562 Return : void 1563 1564This function may execute with the MMU and data caches enabled if the platform 1565port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1566called by the primary CPU. 1567 1568The purpose of this function is to perform any platform initialization 1569specific to BL2. 1570 1571In Arm standard platforms, this function performs security setup, including 1572configuration of the TrustZone controller to allow non-secure masters access 1573to most of DRAM. Part of DRAM is reserved for secure world use. 1574 1575Function : bl2_plat_handle_pre_image_load() [optional] 1576~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1577 1578:: 1579 1580 Argument : unsigned int 1581 Return : int 1582 1583This function can be used by the platforms to update/use image information 1584for given ``image_id``. This function is currently invoked in BL2 before 1585loading each image. 1586 1587Function : bl2_plat_handle_post_image_load() [optional] 1588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1589 1590:: 1591 1592 Argument : unsigned int 1593 Return : int 1594 1595This function can be used by the platforms to update/use image information 1596for given ``image_id``. This function is currently invoked in BL2 after 1597loading each image. 1598 1599Function : bl2_plat_preload_setup [optional] 1600~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1601 1602:: 1603 1604 Argument : void 1605 Return : void 1606 1607This optional function performs any BL2 platform initialization 1608required before image loading, that is not done later in 1609bl2_platform_setup(). Specifically, if support for multiple 1610boot sources is required, it initializes the boot sequence used by 1611plat_try_next_boot_source(). 1612 1613Function : plat_try_next_boot_source() [optional] 1614~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1615 1616:: 1617 1618 Argument : void 1619 Return : int 1620 1621This optional function passes to the next boot source in the redundancy 1622sequence. 1623 1624This function moves the current boot redundancy source to the next 1625element in the boot sequence. If there are no more boot sources then it 1626must return 0, otherwise it must return 1. The default implementation 1627of this always returns 0. 1628 1629Boot Loader Stage 2 (BL2) at EL3 1630-------------------------------- 1631 1632When the platform has a non-TF-A Boot ROM it is desirable to jump 1633directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1634execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design` 1635document for more information. 1636 1637All mandatory functions of BL2 must be implemented, except the functions 1638bl2_early_platform_setup and bl2_el3_plat_arch_setup, because 1639their work is done now by bl2_el3_early_platform_setup and 1640bl2_el3_plat_arch_setup. These functions should generally implement 1641the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. 1642 1643 1644Function : bl2_el3_early_platform_setup() [mandatory] 1645~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1646 1647:: 1648 1649 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1650 Return : void 1651 1652This function executes with the MMU and data caches disabled. It is only called 1653by the primary CPU. This function receives four parameters which can be used 1654by the platform to pass any needed information from the Boot ROM to BL2. 1655 1656On Arm standard platforms, this function does the following: 1657 1658- Initializes a UART (PL011 console), which enables access to the ``printf`` 1659 family of functions in BL2. 1660 1661- Initializes the storage abstraction layer used to load further bootloader 1662 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1663 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1664 1665- Initializes the private variables that define the memory layout used. 1666 1667Function : bl2_el3_plat_arch_setup() [mandatory] 1668~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1669 1670:: 1671 1672 Argument : void 1673 Return : void 1674 1675This function executes with the MMU and data caches disabled. It is only called 1676by the primary CPU. 1677 1678The purpose of this function is to perform any architectural initialization 1679that varies across platforms. 1680 1681On Arm standard platforms, this function enables the MMU. 1682 1683Function : bl2_el3_plat_prepare_exit() [optional] 1684~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1685 1686:: 1687 1688 Argument : void 1689 Return : void 1690 1691This function is called prior to exiting BL2 and run the next image. 1692It should be used to perform platform specific clean up or bookkeeping 1693operations before transferring control to the next image. This function 1694runs with MMU disabled. 1695 1696FWU Boot Loader Stage 2 (BL2U) 1697------------------------------ 1698 1699The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1700process and is executed only by the primary CPU. BL1 passes control to BL2U at 1701``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1702 1703#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure 1704 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. 1705 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U 1706 should be copied from. Subsequent handling of the SCP_BL2U image is 1707 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1708 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1709 1710#. Any platform specific setup required to perform the FWU process. For 1711 example, Arm standard platforms initialize the TZC controller so that the 1712 normal world can access DDR memory. 1713 1714The following functions must be implemented by the platform port to enable 1715BL2U to perform the tasks mentioned above. 1716 1717Function : bl2u_early_platform_setup() [mandatory] 1718~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1719 1720:: 1721 1722 Argument : meminfo *mem_info, void *plat_info 1723 Return : void 1724 1725This function executes with the MMU and data caches disabled. It is only 1726called by the primary CPU. The arguments to this function is the address 1727of the ``meminfo`` structure and platform specific info provided by BL1. 1728 1729The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1730private storage as the original memory may be subsequently overwritten by BL2U. 1731 1732On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1733to extract SCP_BL2U image information, which is then copied into a private 1734variable. 1735 1736Function : bl2u_plat_arch_setup() [mandatory] 1737~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1738 1739:: 1740 1741 Argument : void 1742 Return : void 1743 1744This function executes with the MMU and data caches disabled. It is only 1745called by the primary CPU. 1746 1747The purpose of this function is to perform any architectural initialization 1748that varies across platforms, for example enabling the MMU (since the memory 1749map differs across platforms). 1750 1751Function : bl2u_platform_setup() [mandatory] 1752~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1753 1754:: 1755 1756 Argument : void 1757 Return : void 1758 1759This function may execute with the MMU and data caches enabled if the platform 1760port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1761called by the primary CPU. 1762 1763The purpose of this function is to perform any platform initialization 1764specific to BL2U. 1765 1766In Arm standard platforms, this function performs security setup, including 1767configuration of the TrustZone controller to allow non-secure masters access 1768to most of DRAM. Part of DRAM is reserved for secure world use. 1769 1770Function : bl2u_plat_handle_scp_bl2u() [optional] 1771~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1772 1773:: 1774 1775 Argument : void 1776 Return : int 1777 1778This function is used to perform any platform-specific actions required to 1779handle the SCP firmware. Typically it transfers the image into SCP memory using 1780a platform-specific protocol and waits until SCP executes it and signals to the 1781Application Processor (AP) for BL2U execution to continue. 1782 1783This function returns 0 on success, a negative error code otherwise. 1784This function is included if SCP_BL2U_BASE is defined. 1785 1786Function : bl2_plat_mboot_init() [optional] 1787~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1788 1789:: 1790 1791 Argument : void 1792 Return : void 1793 1794When the MEASURED_BOOT flag is enabled: 1795 1796- This function is used to initialize the backend driver(s) of measured boot. 1797- On the Arm FVP port, this function is used to initialize the Event Log 1798 backend driver with the Event Log buffer information (base address and 1799 size) received from BL1. It results in panic on error. 1800 1801When the MEASURED_BOOT flag is disabled, this function doesn't do anything. 1802 1803Function : bl2_plat_mboot_finish() [optional] 1804~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1805 1806:: 1807 1808 Argument : void 1809 Return : void 1810 1811When the MEASURED_BOOT flag is enabled: 1812 1813- This function is used to finalize the measured boot backend driver(s), 1814 and also, set the information for the next bootloader component to extend 1815 the measurement if needed. 1816- On the Arm FVP port, this function is used to pass the Event Log buffer 1817 information (base address and size) to non-secure(BL33) and trusted OS(BL32) 1818 via nt_fw and tos_fw config respectively. It results in panic on error. 1819 1820When the MEASURED_BOOT flag is disabled, this function doesn't do anything. 1821 1822Boot Loader Stage 3-1 (BL31) 1823---------------------------- 1824 1825During cold boot, the BL31 stage is executed only by the primary CPU. This is 1826determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1827control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1828CPUs. BL31 executes at EL3 and is responsible for: 1829 1830#. Re-initializing all architectural and platform state. Although BL1 performs 1831 some of this initialization, BL31 remains resident in EL3 and must ensure 1832 that EL3 architectural and platform state is completely initialized. It 1833 should make no assumptions about the system state when it receives control. 1834 1835#. Passing control to a normal world BL image, pre-loaded at a platform- 1836 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 1837 populated by BL2 in memory to do this. 1838 1839#. Providing runtime firmware services. Currently, BL31 only implements a 1840 subset of the Power State Coordination Interface (PSCI) API as a runtime 1841 service. See Section 3.3 below for details of porting the PSCI 1842 implementation. 1843 1844#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1845 specific address by BL2. BL31 exports a set of APIs that allow runtime 1846 services to specify the security state in which the next image should be 1847 executed and run the corresponding image. On ARM platforms, BL31 uses the 1848 ``bl_params`` list populated by BL2 in memory to do this. 1849 1850If BL31 is a reset vector, It also needs to handle the reset as specified in 1851section 2.2 before the tasks described above. 1852 1853The following functions must be implemented by the platform port to enable BL31 1854to perform the above tasks. 1855 1856Function : bl31_early_platform_setup2() [mandatory] 1857~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1858 1859:: 1860 1861 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1862 Return : void 1863 1864This function executes with the MMU and data caches disabled. It is only called 1865by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 1866platform specific. 1867 1868In Arm standard platforms, the arguments received are : 1869 1870 arg0 - The pointer to the head of `bl_params_t` list 1871 which is list of executable images following BL31, 1872 1873 arg1 - Points to load address of SOC_FW_CONFIG if present 1874 except in case of Arm FVP and Juno platform. 1875 1876 In case of Arm FVP and Juno platform, points to load address 1877 of FW_CONFIG. 1878 1879 arg2 - Points to load address of HW_CONFIG if present 1880 1881 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 1882 used in release builds. 1883 1884The function runs through the `bl_param_t` list and extracts the entry point 1885information for BL32 and BL33. It also performs the following: 1886 1887- Initialize a UART (PL011 console), which enables access to the ``printf`` 1888 family of functions in BL31. 1889 1890- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1891 CCI slave interface corresponding to the cluster that includes the primary 1892 CPU. 1893 1894Function : bl31_plat_arch_setup() [mandatory] 1895~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1896 1897:: 1898 1899 Argument : void 1900 Return : void 1901 1902This function executes with the MMU and data caches disabled. It is only called 1903by the primary CPU. 1904 1905The purpose of this function is to perform any architectural initialization 1906that varies across platforms. 1907 1908On Arm standard platforms, this function enables the MMU. 1909 1910Function : bl31_platform_setup() [mandatory] 1911~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1912 1913:: 1914 1915 Argument : void 1916 Return : void 1917 1918This function may execute with the MMU and data caches enabled if the platform 1919port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1920called by the primary CPU. 1921 1922The purpose of this function is to complete platform initialization so that both 1923BL31 runtime services and normal world software can function correctly. 1924 1925On Arm standard platforms, this function does the following: 1926 1927- Initialize the generic interrupt controller. 1928 1929 Depending on the GIC driver selected by the platform, the appropriate GICv2 1930 or GICv3 initialization will be done, which mainly consists of: 1931 1932 - Enable secure interrupts in the GIC CPU interface. 1933 - Disable the legacy interrupt bypass mechanism. 1934 - Configure the priority mask register to allow interrupts of all priorities 1935 to be signaled to the CPU interface. 1936 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1937 - Target all secure SPIs to CPU0. 1938 - Enable these secure interrupts in the GIC distributor. 1939 - Configure all other interrupts as non-secure. 1940 - Enable signaling of secure interrupts in the GIC distributor. 1941 1942- Enable system-level implementation of the generic timer counter through the 1943 memory mapped interface. 1944 1945- Grant access to the system counter timer module 1946 1947- Initialize the power controller device. 1948 1949 In particular, initialise the locks that prevent concurrent accesses to the 1950 power controller device. 1951 1952Function : bl31_plat_runtime_setup() [optional] 1953~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1954 1955:: 1956 1957 Argument : void 1958 Return : void 1959 1960The purpose of this function is allow the platform to perform any BL31 runtime 1961setup just prior to BL31 exit during cold boot. The default weak 1962implementation of this function will invoke ``console_switch_state()`` to switch 1963console output to consoles marked for use in the ``runtime`` state. 1964 1965Function : bl31_plat_get_next_image_ep_info() [mandatory] 1966~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1967 1968:: 1969 1970 Argument : uint32_t 1971 Return : entry_point_info * 1972 1973This function may execute with the MMU and data caches enabled if the platform 1974port does the necessary initializations in ``bl31_plat_arch_setup()``. 1975 1976This function is called by ``bl31_main()`` to retrieve information provided by 1977BL2 for the next image in the security state specified by the argument. BL31 1978uses this information to pass control to that image in the specified security 1979state. This function must return a pointer to the ``entry_point_info`` structure 1980(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 1981should return NULL otherwise. 1982 1983Function : bl31_plat_enable_mmu [optional] 1984~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1985 1986:: 1987 1988 Argument : uint32_t 1989 Return : void 1990 1991This function enables the MMU. The boot code calls this function with MMU and 1992caches disabled. This function should program necessary registers to enable 1993translation, and upon return, the MMU on the calling PE must be enabled. 1994 1995The function must honor flags passed in the first argument. These flags are 1996defined by the translation library, and can be found in the file 1997``include/lib/xlat_tables/xlat_mmu_helpers.h``. 1998 1999On DynamIQ systems, this function must not use stack while enabling MMU, which 2000is how the function in xlat table library version 2 is implemented. 2001 2002Function : plat_init_apkey [optional] 2003~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2004 2005:: 2006 2007 Argument : void 2008 Return : uint128_t 2009 2010This function returns the 128-bit value which can be used to program ARMv8.3 2011pointer authentication keys. 2012 2013The value should be obtained from a reliable source of randomness. 2014 2015This function is only needed if ARMv8.3 pointer authentication is used in the 2016Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero. 2017 2018Function : plat_get_syscnt_freq2() [mandatory] 2019~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2020 2021:: 2022 2023 Argument : void 2024 Return : unsigned int 2025 2026This function is used by the architecture setup code to retrieve the counter 2027frequency for the CPU's generic timer. This value will be programmed into the 2028``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2029of the system counter, which is retrieved from the first entry in the frequency 2030modes table. 2031 2032Function : plat_arm_set_twedel_scr_el3() [optional] 2033~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2034 2035:: 2036 2037 Argument : void 2038 Return : uint32_t 2039 2040This function is used in v8.6+ systems to set the WFE trap delay value in 2041SCR_EL3. If this function returns TWED_DISABLED or is left unimplemented, this 2042feature is not enabled. The only hook provided is to set the TWED fields in 2043SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to adjust 2044the WFE trap delays in lower ELs and these fields should be set by the 2045appropriate EL2 or EL1 code depending on the platform configuration. 2046 2047#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] 2048~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2049 2050When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2051bytes) aligned to the cache line boundary that should be allocated per-cpu to 2052accommodate all the bakery locks. 2053 2054If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2055calculates the size of the ``bakery_lock`` input section, aligns it to the 2056nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2057and stores the result in a linker symbol. This constant prevents a platform 2058from relying on the linker and provide a more efficient mechanism for 2059accessing per-cpu bakery lock information. 2060 2061If this constant is defined and its value is not equal to the value 2062calculated by the linker then a link time assertion is raised. A compile time 2063assertion is raised if the value of the constant is not aligned to the cache 2064line boundary. 2065 2066.. _porting_guide_sdei_requirements: 2067 2068SDEI porting requirements 2069~~~~~~~~~~~~~~~~~~~~~~~~~ 2070 2071The |SDEI| dispatcher requires the platform to provide the following macros 2072and functions, of which some are optional, and some others mandatory. 2073 2074Macros 2075...... 2076 2077Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2078^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2079 2080This macro must be defined to the EL3 exception priority level associated with 2081Normal |SDEI| events on the platform. This must have a higher value 2082(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2083 2084Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2085^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2086 2087This macro must be defined to the EL3 exception priority level associated with 2088Critical |SDEI| events on the platform. This must have a lower value 2089(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2090 2091**Note**: |SDEI| exception priorities must be the lowest among Secure 2092priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must 2093be higher than Normal |SDEI| priority. 2094 2095Functions 2096......... 2097 2098Function: int plat_sdei_validate_entry_point() [optional] 2099^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2100 2101:: 2102 2103 Argument: uintptr_t ep, unsigned int client_mode 2104 Return: int 2105 2106This function validates the entry point address of the event handler provided by 2107the client for both event registration and *Complete and Resume* |SDEI| calls. 2108The function ensures that the address is valid in the client translation regime. 2109 2110The second argument is the exception level that the client is executing in. It 2111can be Non-Secure EL1 or Non-Secure EL2. 2112 2113The function must return ``0`` for successful validation, or ``-1`` upon failure. 2114 2115The default implementation always returns ``0``. On Arm platforms, this function 2116translates the entry point address within the client translation regime and 2117further ensures that the resulting physical address is located in Non-secure 2118DRAM. 2119 2120Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2121^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2122 2123:: 2124 2125 Argument: uint64_t 2126 Argument: unsigned int 2127 Return: void 2128 2129|SDEI| specification requires that a PE comes out of reset with the events 2130masked. The client therefore is expected to call ``PE_UNMASK`` to unmask 2131|SDEI| events on the PE. No |SDEI| events can be dispatched until such 2132time. 2133 2134Should a PE receive an interrupt that was bound to an |SDEI| event while the 2135events are masked on the PE, the dispatcher implementation invokes the function 2136``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2137interrupt and the interrupt ID are passed as parameters. 2138 2139The default implementation only prints out a warning message. 2140 2141.. _porting_guide_trng_requirements: 2142 2143TRNG porting requirements 2144~~~~~~~~~~~~~~~~~~~~~~~~~ 2145 2146The |TRNG| backend requires the platform to provide the following values 2147and mandatory functions. 2148 2149Values 2150...... 2151 2152value: uuid_t plat_trng_uuid [mandatory] 2153^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2154 2155This value must be defined to the UUID of the TRNG backend that is specific to 2156the hardware after ``plat_trng_setup`` function is called. This value must 2157conform to the SMCCC calling convention; The most significant 32 bits of the 2158UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in 2159w0 indicates failure to get a TRNG source. 2160 2161Functions 2162......... 2163 2164Function: void plat_entropy_setup(void) [mandatory] 2165^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2166 2167:: 2168 2169 Argument: none 2170 Return: none 2171 2172This function is expected to do platform-specific initialization of any TRNG 2173hardware. This may include generating a UUID from a hardware-specific seed. 2174 2175Function: bool plat_get_entropy(uint64_t \*out) [mandatory] 2176^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2177 2178:: 2179 2180 Argument: uint64_t * 2181 Return: bool 2182 Out : when the return value is true, the entropy has been written into the 2183 storage pointed to 2184 2185This function writes entropy into storage provided by the caller. If no entropy 2186is available, it must return false and the storage must not be written. 2187 2188Power State Coordination Interface (in BL31) 2189-------------------------------------------- 2190 2191The TF-A implementation of the PSCI API is based around the concept of a 2192*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2193share some state on which power management operations can be performed as 2194specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2195a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2196*power domains* are arranged in a hierarchical tree structure and each 2197*power domain* can be identified in a system by the cpu index of any CPU that 2198is part of that domain and a *power domain level*. A processing element (for 2199example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2200logical grouping of CPUs that share some state, then level 1 is that group of 2201CPUs (for example, a cluster), and level 2 is a group of clusters (for 2202example, the system). More details on the power domain topology and its 2203organization can be found in :ref:`PSCI Power Domain Tree Structure`. 2204 2205BL31's platform initialization code exports a pointer to the platform-specific 2206power management operations required for the PSCI implementation to function 2207correctly. This information is populated in the ``plat_psci_ops`` structure. The 2208PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2209power management operations on the power domains. For example, the target 2210CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2211handler (if present) is called for the CPU power domain. 2212 2213The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2214describe composite power states specific to a platform. The PSCI implementation 2215defines a generic representation of the power-state parameter, which is an 2216array of local power states where each index corresponds to a power domain 2217level. Each entry contains the local power state the power domain at that power 2218level could enter. It depends on the ``validate_power_state()`` handler to 2219convert the power-state parameter (possibly encoding a composite power state) 2220passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2221 2222The following functions form part of platform port of PSCI functionality. 2223 2224Function : plat_psci_stat_accounting_start() [optional] 2225~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2226 2227:: 2228 2229 Argument : const psci_power_state_t * 2230 Return : void 2231 2232This is an optional hook that platforms can implement for residency statistics 2233accounting before entering a low power state. The ``pwr_domain_state`` field of 2234``state_info`` (first argument) can be inspected if stat accounting is done 2235differently at CPU level versus higher levels. As an example, if the element at 2236index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2237state, special hardware logic may be programmed in order to keep track of the 2238residency statistics. For higher levels (array indices > 0), the residency 2239statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2240default implementation will use PMF to capture timestamps. 2241 2242Function : plat_psci_stat_accounting_stop() [optional] 2243~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2244 2245:: 2246 2247 Argument : const psci_power_state_t * 2248 Return : void 2249 2250This is an optional hook that platforms can implement for residency statistics 2251accounting after exiting from a low power state. The ``pwr_domain_state`` field 2252of ``state_info`` (first argument) can be inspected if stat accounting is done 2253differently at CPU level versus higher levels. As an example, if the element at 2254index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2255state, special hardware logic may be programmed in order to keep track of the 2256residency statistics. For higher levels (array indices > 0), the residency 2257statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2258default implementation will use PMF to capture timestamps. 2259 2260Function : plat_psci_stat_get_residency() [optional] 2261~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2262 2263:: 2264 2265 Argument : unsigned int, const psci_power_state_t *, unsigned int 2266 Return : u_register_t 2267 2268This is an optional interface that is is invoked after resuming from a low power 2269state and provides the time spent resident in that low power state by the power 2270domain at a particular power domain level. When a CPU wakes up from suspend, 2271all its parent power domain levels are also woken up. The generic PSCI code 2272invokes this function for each parent power domain that is resumed and it 2273identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2274argument) describes the low power state that the power domain has resumed from. 2275The current CPU is the first CPU in the power domain to resume from the low 2276power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2277CPU in the power domain to suspend and may be needed to calculate the residency 2278for that power domain. 2279 2280Function : plat_get_target_pwr_state() [optional] 2281~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2282 2283:: 2284 2285 Argument : unsigned int, const plat_local_state_t *, unsigned int 2286 Return : plat_local_state_t 2287 2288The PSCI generic code uses this function to let the platform participate in 2289state coordination during a power management operation. The function is passed 2290a pointer to an array of platform specific local power state ``states`` (second 2291argument) which contains the requested power state for each CPU at a particular 2292power domain level ``lvl`` (first argument) within the power domain. The function 2293is expected to traverse this array of upto ``ncpus`` (third argument) and return 2294a coordinated target power state by the comparing all the requested power 2295states. The target power state should not be deeper than any of the requested 2296power states. 2297 2298A weak definition of this API is provided by default wherein it assumes 2299that the platform assigns a local state value in order of increasing depth 2300of the power state i.e. for two power states X & Y, if X < Y 2301then X represents a shallower power state than Y. As a result, the 2302coordinated target local power state for a power domain will be the minimum 2303of the requested local power state values. 2304 2305Function : plat_get_power_domain_tree_desc() [mandatory] 2306~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2307 2308:: 2309 2310 Argument : void 2311 Return : const unsigned char * 2312 2313This function returns a pointer to the byte array containing the power domain 2314topology tree description. The format and method to construct this array are 2315described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI 2316initialization code requires this array to be described by the platform, either 2317statically or dynamically, to initialize the power domain topology tree. In case 2318the array is populated dynamically, then plat_core_pos_by_mpidr() and 2319plat_my_core_pos() should also be implemented suitably so that the topology tree 2320description matches the CPU indices returned by these APIs. These APIs together 2321form the platform interface for the PSCI topology framework. 2322 2323Function : plat_setup_psci_ops() [mandatory] 2324~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2325 2326:: 2327 2328 Argument : uintptr_t, const plat_psci_ops ** 2329 Return : int 2330 2331This function may execute with the MMU and data caches enabled if the platform 2332port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2333called by the primary CPU. 2334 2335This function is called by PSCI initialization code. Its purpose is to let 2336the platform layer know about the warm boot entrypoint through the 2337``sec_entrypoint`` (first argument) and to export handler routines for 2338platform-specific psci power management actions by populating the passed 2339pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2340 2341A description of each member of this structure is given below. Please refer to 2342the Arm FVP specific implementation of these handlers in 2343``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the 2344platform wants to support, the associated operation or operations in this 2345structure must be provided and implemented (Refer section 4 of 2346:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI 2347function in a platform port, the operation should be removed from this 2348structure instead of providing an empty implementation. 2349 2350plat_psci_ops.cpu_standby() 2351........................... 2352 2353Perform the platform-specific actions to enter the standby state for a cpu 2354indicated by the passed argument. This provides a fast path for CPU standby 2355wherein overheads of PSCI state management and lock acquisition is avoided. 2356For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2357the suspend state type specified in the ``power-state`` parameter should be 2358STANDBY and the target power domain level specified should be the CPU. The 2359handler should put the CPU into a low power retention state (usually by 2360issuing a wfi instruction) and ensure that it can be woken up from that 2361state by a normal interrupt. The generic code expects the handler to succeed. 2362 2363plat_psci_ops.pwr_domain_on() 2364............................. 2365 2366Perform the platform specific actions to power on a CPU, specified 2367by the ``MPIDR`` (first argument). The generic code expects the platform to 2368return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. 2369 2370plat_psci_ops.pwr_domain_off() 2371.............................. 2372 2373Perform the platform specific actions to prepare to power off the calling CPU 2374and its higher parent power domain levels as indicated by the ``target_state`` 2375(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2376 2377The ``target_state`` encodes the platform coordinated target local power states 2378for the CPU power domain and its parent power domain levels. The handler 2379needs to perform power management operation corresponding to the local state 2380at each power level. 2381 2382For this handler, the local power state for the CPU power domain will be a 2383power down state where as it could be either power down, retention or run state 2384for the higher power domain levels depending on the result of state 2385coordination. The generic code expects the handler to succeed. 2386 2387plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] 2388........................................................... 2389 2390This optional function may be used as a performance optimization to replace 2391or complement pwr_domain_suspend() on some platforms. Its calling semantics 2392are identical to pwr_domain_suspend(), except the PSCI implementation only 2393calls this function when suspending to a power down state, and it guarantees 2394that data caches are enabled. 2395 2396When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2397before calling pwr_domain_suspend(). If the target_state corresponds to a 2398power down state and it is safe to perform some or all of the platform 2399specific actions in that function with data caches enabled, it may be more 2400efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2401= 1, data caches remain enabled throughout, and so there is no advantage to 2402moving platform specific actions to this function. 2403 2404plat_psci_ops.pwr_domain_suspend() 2405.................................. 2406 2407Perform the platform specific actions to prepare to suspend the calling 2408CPU and its higher parent power domain levels as indicated by the 2409``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2410API implementation. 2411 2412The ``target_state`` has a similar meaning as described in 2413the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2414target local power states for the CPU power domain and its parent 2415power domain levels. The handler needs to perform power management operation 2416corresponding to the local state at each power level. The generic code 2417expects the handler to succeed. 2418 2419The difference between turning a power domain off versus suspending it is that 2420in the former case, the power domain is expected to re-initialize its state 2421when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2422case, the power domain is expected to save enough state so that it can resume 2423execution by restoring this state when its powered on (see 2424``pwr_domain_suspend_finish()``). 2425 2426When suspending a core, the platform can also choose to power off the GICv3 2427Redistributor and ITS through an implementation-defined sequence. To achieve 2428this safely, the ITS context must be saved first. The architectural part is 2429implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2430sequence is implementation defined and it is therefore the responsibility of 2431the platform code to implement the necessary sequence. Then the GIC 2432Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2433Powering off the Redistributor requires the implementation to support it and it 2434is the responsibility of the platform code to execute the right implementation 2435defined sequence. 2436 2437When a system suspend is requested, the platform can also make use of the 2438``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2439it has saved the context of the Redistributors and ITS of all the cores in the 2440system. The context of the Distributor can be large and may require it to be 2441allocated in a special area if it cannot fit in the platform's global static 2442data, for example in DRAM. The Distributor can then be powered down using an 2443implementation-defined sequence. 2444 2445plat_psci_ops.pwr_domain_pwr_down_wfi() 2446....................................... 2447 2448This is an optional function and, if implemented, is expected to perform 2449platform specific actions including the ``wfi`` invocation which allows the 2450CPU to powerdown. Since this function is invoked outside the PSCI locks, 2451the actions performed in this hook must be local to the CPU or the platform 2452must ensure that races between multiple CPUs cannot occur. 2453 2454The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2455operation and it encodes the platform coordinated target local power states for 2456the CPU power domain and its parent power domain levels. This function must 2457not return back to the caller. 2458 2459If this function is not implemented by the platform, PSCI generic 2460implementation invokes ``psci_power_down_wfi()`` for power down. 2461 2462plat_psci_ops.pwr_domain_on_finish() 2463.................................... 2464 2465This function is called by the PSCI implementation after the calling CPU is 2466powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2467It performs the platform-specific setup required to initialize enough state for 2468this CPU to enter the normal world and also provide secure runtime firmware 2469services. 2470 2471The ``target_state`` (first argument) is the prior state of the power domains 2472immediately before the CPU was turned on. It indicates which power domains 2473above the CPU might require initialization due to having previously been in 2474low power states. The generic code expects the handler to succeed. 2475 2476plat_psci_ops.pwr_domain_on_finish_late() [optional] 2477........................................................... 2478 2479This optional function is called by the PSCI implementation after the calling 2480CPU is fully powered on with respective data caches enabled. The calling CPU and 2481the associated cluster are guaranteed to be participating in coherency. This 2482function gives the flexibility to perform any platform-specific actions safely, 2483such as initialization or modification of shared data structures, without the 2484overhead of explicit cache maintainace operations. 2485 2486The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` 2487operation. The generic code expects the handler to succeed. 2488 2489plat_psci_ops.pwr_domain_suspend_finish() 2490......................................... 2491 2492This function is called by the PSCI implementation after the calling CPU is 2493powered on and released from reset in response to an asynchronous wakeup 2494event, for example a timer interrupt that was programmed by the CPU during the 2495``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2496setup required to restore the saved state for this CPU to resume execution 2497in the normal world and also provide secure runtime firmware services. 2498 2499The ``target_state`` (first argument) has a similar meaning as described in 2500the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2501to succeed. 2502 2503If the Distributor, Redistributors or ITS have been powered off as part of a 2504suspend, their context must be restored in this function in the reverse order 2505to how they were saved during suspend sequence. 2506 2507plat_psci_ops.system_off() 2508.......................... 2509 2510This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2511call. It performs the platform-specific system poweroff sequence after 2512notifying the Secure Payload Dispatcher. 2513 2514plat_psci_ops.system_reset() 2515............................ 2516 2517This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2518call. It performs the platform-specific system reset sequence after 2519notifying the Secure Payload Dispatcher. 2520 2521plat_psci_ops.validate_power_state() 2522.................................... 2523 2524This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2525call to validate the ``power_state`` parameter of the PSCI API and if valid, 2526populate it in ``req_state`` (second argument) array as power domain level 2527specific local states. If the ``power_state`` is invalid, the platform must 2528return PSCI_E_INVALID_PARAMS as error, which is propagated back to the 2529normal world PSCI client. 2530 2531plat_psci_ops.validate_ns_entrypoint() 2532...................................... 2533 2534This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2535``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2536parameter passed by the normal world. If the ``entry_point`` is invalid, 2537the platform must return PSCI_E_INVALID_ADDRESS as error, which is 2538propagated back to the normal world PSCI client. 2539 2540plat_psci_ops.get_sys_suspend_power_state() 2541........................................... 2542 2543This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2544call to get the ``req_state`` parameter from platform which encodes the power 2545domain level specific local states to suspend to system affinity level. The 2546``req_state`` will be utilized to do the PSCI state coordination and 2547``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2548enter system suspend. 2549 2550plat_psci_ops.get_pwr_lvl_state_idx() 2551..................................... 2552 2553This is an optional function and, if implemented, is invoked by the PSCI 2554implementation to convert the ``local_state`` (first argument) at a specified 2555``pwr_lvl`` (second argument) to an index between 0 and 2556``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2557supports more than two local power states at each power domain level, that is 2558``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2559local power states. 2560 2561plat_psci_ops.translate_power_state_by_mpidr() 2562.............................................. 2563 2564This is an optional function and, if implemented, verifies the ``power_state`` 2565(second argument) parameter of the PSCI API corresponding to a target power 2566domain. The target power domain is identified by using both ``MPIDR`` (first 2567argument) and the power domain level encoded in ``power_state``. The power domain 2568level specific local states are to be extracted from ``power_state`` and be 2569populated in the ``output_state`` (third argument) array. The functionality 2570is similar to the ``validate_power_state`` function described above and is 2571envisaged to be used in case the validity of ``power_state`` depend on the 2572targeted power domain. If the ``power_state`` is invalid for the targeted power 2573domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this 2574function is not implemented, then the generic implementation relies on 2575``validate_power_state`` function to translate the ``power_state``. 2576 2577This function can also be used in case the platform wants to support local 2578power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY 2579APIs as described in Section 5.18 of `PSCI`_. 2580 2581plat_psci_ops.get_node_hw_state() 2582................................. 2583 2584This is an optional function. If implemented this function is intended to return 2585the power state of a node (identified by the first parameter, the ``MPIDR``) in 2586the power domain topology (identified by the second parameter, ``power_level``), 2587as retrieved from a power controller or equivalent component on the platform. 2588Upon successful completion, the implementation must map and return the final 2589status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2590must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2591appropriate. 2592 2593Implementations are not expected to handle ``power_levels`` greater than 2594``PLAT_MAX_PWR_LVL``. 2595 2596plat_psci_ops.system_reset2() 2597............................. 2598 2599This is an optional function. If implemented this function is 2600called during the ``SYSTEM_RESET2`` call to perform a reset 2601based on the first parameter ``reset_type`` as specified in 2602`PSCI`_. The parameter ``cookie`` can be used to pass additional 2603reset information. If the ``reset_type`` is not supported, the 2604function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2605resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2606and vendor reset can return other PSCI error codes as defined 2607in `PSCI`_. On success this function will not return. 2608 2609plat_psci_ops.write_mem_protect() 2610................................. 2611 2612This is an optional function. If implemented it enables or disables the 2613``MEM_PROTECT`` functionality based on the value of ``val``. 2614A non-zero value enables ``MEM_PROTECT`` and a value of zero 2615disables it. Upon encountering failures it must return a negative value 2616and on success it must return 0. 2617 2618plat_psci_ops.read_mem_protect() 2619................................ 2620 2621This is an optional function. If implemented it returns the current 2622state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2623failures it must return a negative value and on success it must 2624return 0. 2625 2626plat_psci_ops.mem_protect_chk() 2627............................... 2628 2629This is an optional function. If implemented it checks if a memory 2630region defined by a base address ``base`` and with a size of ``length`` 2631bytes is protected by ``MEM_PROTECT``. If the region is protected 2632then it must return 0, otherwise it must return a negative number. 2633 2634.. _porting_guide_imf_in_bl31: 2635 2636Interrupt Management framework (in BL31) 2637---------------------------------------- 2638 2639BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2640generated in either security state and targeted to EL1 or EL2 in the non-secure 2641state or EL3/S-EL1 in the secure state. The design of this framework is 2642described in the :ref:`Interrupt Management Framework` 2643 2644A platform should export the following APIs to support the IMF. The following 2645text briefly describes each API and its implementation in Arm standard 2646platforms. The API implementation depends upon the type of interrupt controller 2647present in the platform. Arm standard platform layer supports both 2648`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2649and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2650FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2651``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more 2652details). 2653 2654See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`. 2655 2656Function : plat_interrupt_type_to_line() [mandatory] 2657~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2658 2659:: 2660 2661 Argument : uint32_t, uint32_t 2662 Return : uint32_t 2663 2664The Arm processor signals an interrupt exception either through the IRQ or FIQ 2665interrupt line. The specific line that is signaled depends on how the interrupt 2666controller (IC) reports different interrupt types from an execution context in 2667either security state. The IMF uses this API to determine which interrupt line 2668the platform IC uses to signal each type of interrupt supported by the framework 2669from a given security state. This API must be invoked at EL3. 2670 2671The first parameter will be one of the ``INTR_TYPE_*`` values (see 2672:ref:`Interrupt Management Framework`) indicating the target type of the 2673interrupt, the second parameter is the security state of the originating 2674execution context. The return result is the bit position in the ``SCR_EL3`` 2675register of the respective interrupt trap: IRQ=1, FIQ=2. 2676 2677In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 2678configured as FIQs and Non-secure interrupts as IRQs from either security 2679state. 2680 2681In the case of Arm standard platforms using GICv3, the interrupt line to be 2682configured depends on the security state of the execution context when the 2683interrupt is signalled and are as follows: 2684 2685- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2686 NS-EL0/1/2 context. 2687- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2688 in the NS-EL0/1/2 context. 2689- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2690 context. 2691 2692Function : plat_ic_get_pending_interrupt_type() [mandatory] 2693~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2694 2695:: 2696 2697 Argument : void 2698 Return : uint32_t 2699 2700This API returns the type of the highest priority pending interrupt at the 2701platform IC. The IMF uses the interrupt type to retrieve the corresponding 2702handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2703pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2704``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2705 2706In the case of Arm standard platforms using GICv2, the *Highest Priority 2707Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2708the pending interrupt. The type of interrupt depends upon the id value as 2709follows. 2710 2711#. id < 1022 is reported as a S-EL1 interrupt 2712#. id = 1022 is reported as a Non-secure interrupt. 2713#. id = 1023 is reported as an invalid interrupt type. 2714 2715In the case of Arm standard platforms using GICv3, the system register 2716``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2717is read to determine the id of the pending interrupt. The type of interrupt 2718depends upon the id value as follows. 2719 2720#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2721#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2722#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2723#. All other interrupt id's are reported as EL3 interrupt. 2724 2725Function : plat_ic_get_pending_interrupt_id() [mandatory] 2726~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2727 2728:: 2729 2730 Argument : void 2731 Return : uint32_t 2732 2733This API returns the id of the highest priority pending interrupt at the 2734platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2735pending. 2736 2737In the case of Arm standard platforms using GICv2, the *Highest Priority 2738Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2739pending interrupt. The id that is returned by API depends upon the value of 2740the id read from the interrupt controller as follows. 2741 2742#. id < 1022. id is returned as is. 2743#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2744 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2745 This id is returned by the API. 2746#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2747 2748In the case of Arm standard platforms using GICv3, if the API is invoked from 2749EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2750group 0 Register*, is read to determine the id of the pending interrupt. The id 2751that is returned by API depends upon the value of the id read from the 2752interrupt controller as follows. 2753 2754#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2755#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2756 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2757 Register* is read to determine the id of the group 1 interrupt. This id 2758 is returned by the API as long as it is a valid interrupt id 2759#. If the id is any of the special interrupt identifiers, 2760 ``INTR_ID_UNAVAILABLE`` is returned. 2761 2762When the API invoked from S-EL1 for GICv3 systems, the id read from system 2763register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2764Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else 2765``INTR_ID_UNAVAILABLE`` is returned. 2766 2767Function : plat_ic_acknowledge_interrupt() [mandatory] 2768~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2769 2770:: 2771 2772 Argument : void 2773 Return : uint32_t 2774 2775This API is used by the CPU to indicate to the platform IC that processing of 2776the highest pending interrupt has begun. It should return the raw, unmodified 2777value obtained from the interrupt controller when acknowledging an interrupt. 2778The actual interrupt number shall be extracted from this raw value using the API 2779`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`. 2780 2781This function in Arm standard platforms using GICv2, reads the *Interrupt 2782Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2783priority pending interrupt from pending to active in the interrupt controller. 2784It returns the value read from the ``GICC_IAR``, unmodified. 2785 2786In the case of Arm standard platforms using GICv3, if the API is invoked 2787from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2788Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2789reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2790group 1*. The read changes the state of the highest pending interrupt from 2791pending to active in the interrupt controller. The value read is returned 2792unmodified. 2793 2794The TSP uses this API to start processing of the secure physical timer 2795interrupt. 2796 2797Function : plat_ic_end_of_interrupt() [mandatory] 2798~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2799 2800:: 2801 2802 Argument : uint32_t 2803 Return : void 2804 2805This API is used by the CPU to indicate to the platform IC that processing of 2806the interrupt corresponding to the id (passed as the parameter) has 2807finished. The id should be the same as the id returned by the 2808``plat_ic_acknowledge_interrupt()`` API. 2809 2810Arm standard platforms write the id to the *End of Interrupt Register* 2811(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2812system register in case of GICv3 depending on where the API is invoked from, 2813EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2814controller. 2815 2816The TSP uses this API to finish processing of the secure physical timer 2817interrupt. 2818 2819Function : plat_ic_get_interrupt_type() [mandatory] 2820~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2821 2822:: 2823 2824 Argument : uint32_t 2825 Return : uint32_t 2826 2827This API returns the type of the interrupt id passed as the parameter. 2828``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2829interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2830returned depending upon how the interrupt has been configured by the platform 2831IC. This API must be invoked at EL3. 2832 2833Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2834and Non-secure interrupts as Group1 interrupts. It reads the group value 2835corresponding to the interrupt id from the relevant *Interrupt Group Register* 2836(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2837 2838In the case of Arm standard platforms using GICv3, both the *Interrupt Group 2839Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2840(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2841as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2842 2843Crash Reporting mechanism (in BL31) 2844----------------------------------- 2845 2846BL31 implements a crash reporting mechanism which prints the various registers 2847of the CPU to enable quick crash analysis and debugging. This mechanism relies 2848on the platform implementing ``plat_crash_console_init``, 2849``plat_crash_console_putc`` and ``plat_crash_console_flush``. 2850 2851The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample 2852implementation of all of them. Platforms may include this file to their 2853makefiles in order to benefit from them. By default, they will cause the crash 2854output to be routed over the normal console infrastructure and get printed on 2855consoles configured to output in crash state. ``console_set_scope()`` can be 2856used to control whether a console is used for crash output. 2857 2858.. note:: 2859 Platforms are responsible for making sure that they only mark consoles for 2860 use in the crash scope that are able to support this, i.e. that are written 2861 in assembly and conform with the register clobber rules for putc() 2862 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks. 2863 2864In some cases (such as debugging very early crashes that happen before the 2865normal boot console can be set up), platforms may want to control crash output 2866more explicitly. These platforms may instead provide custom implementations for 2867these. They are executed outside of a C environment and without a stack. Many 2868console drivers provide functions named ``console_xxx_core_init/putc/flush`` 2869that are designed to be used by these functions. See Arm platforms (like juno) 2870for an example of this. 2871 2872Function : plat_crash_console_init [mandatory] 2873~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2874 2875:: 2876 2877 Argument : void 2878 Return : int 2879 2880This API is used by the crash reporting mechanism to initialize the crash 2881console. It must only use the general purpose registers x0 through x7 to do the 2882initialization and returns 1 on success. 2883 2884Function : plat_crash_console_putc [mandatory] 2885~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2886 2887:: 2888 2889 Argument : int 2890 Return : int 2891 2892This API is used by the crash reporting mechanism to print a character on the 2893designated crash console. It must only use general purpose registers x1 and 2894x2 to do its work. The parameter and the return value are in general purpose 2895register x0. 2896 2897Function : plat_crash_console_flush [mandatory] 2898~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2899 2900:: 2901 2902 Argument : void 2903 Return : void 2904 2905This API is used by the crash reporting mechanism to force write of all buffered 2906data on the designated crash console. It should only use general purpose 2907registers x0 through x5 to do its work. 2908 2909.. _External Abort handling and RAS Support: 2910 2911External Abort handling and RAS Support 2912--------------------------------------- 2913 2914Function : plat_ea_handler 2915~~~~~~~~~~~~~~~~~~~~~~~~~~ 2916 2917:: 2918 2919 Argument : int 2920 Argument : uint64_t 2921 Argument : void * 2922 Argument : void * 2923 Argument : uint64_t 2924 Return : void 2925 2926This function is invoked by the RAS framework for the platform to handle an 2927External Abort received at EL3. The intention of the function is to attempt to 2928resolve the cause of External Abort and return; if that's not possible, to 2929initiate orderly shutdown of the system. 2930 2931The first parameter (``int ea_reason``) indicates the reason for External Abort. 2932Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 2933 2934The second parameter (``uint64_t syndrome``) is the respective syndrome 2935presented to EL3 after having received the External Abort. Depending on the 2936nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 2937can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 2938 2939The third parameter (``void *cookie``) is unused for now. The fourth parameter 2940(``void *handle``) is a pointer to the preempted context. The fifth parameter 2941(``uint64_t flags``) indicates the preempted security state. These parameters 2942are received from the top-level exception handler. 2943 2944If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this 2945function iterates through RAS handlers registered by the platform. If any of the 2946RAS handlers resolve the External Abort, no further action is taken. 2947 2948If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers 2949could resolve the External Abort, the default implementation prints an error 2950message, and panics. 2951 2952Function : plat_handle_uncontainable_ea 2953~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2954 2955:: 2956 2957 Argument : int 2958 Argument : uint64_t 2959 Return : void 2960 2961This function is invoked by the RAS framework when an External Abort of 2962Uncontainable type is received at EL3. Due to the critical nature of 2963Uncontainable errors, the intention of this function is to initiate orderly 2964shutdown of the system, and is not expected to return. 2965 2966This function must be implemented in assembly. 2967 2968The first and second parameters are the same as that of ``plat_ea_handler``. 2969 2970The default implementation of this function calls 2971``report_unhandled_exception``. 2972 2973Function : plat_handle_double_fault 2974~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2975 2976:: 2977 2978 Argument : int 2979 Argument : uint64_t 2980 Return : void 2981 2982This function is invoked by the RAS framework when another External Abort is 2983received at EL3 while one is already being handled. I.e., a call to 2984``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 2985this function is to initiate orderly shutdown of the system, and is not expected 2986recover or return. 2987 2988This function must be implemented in assembly. 2989 2990The first and second parameters are the same as that of ``plat_ea_handler``. 2991 2992The default implementation of this function calls 2993``report_unhandled_exception``. 2994 2995Function : plat_handle_el3_ea 2996~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2997 2998:: 2999 3000 Return : void 3001 3002This function is invoked when an External Abort is received while executing in 3003EL3. Due to its critical nature, the intention of this function is to initiate 3004orderly shutdown of the system, and is not expected recover or return. 3005 3006This function must be implemented in assembly. 3007 3008The default implementation of this function calls 3009``report_unhandled_exception``. 3010 3011Build flags 3012----------- 3013 3014There are some build flags which can be defined by the platform to control 3015inclusion or exclusion of certain BL stages from the FIP image. These flags 3016need to be defined in the platform makefile which will get included by the 3017build system. 3018 3019- **NEED_BL33** 3020 By default, this flag is defined ``yes`` by the build system and ``BL33`` 3021 build option should be supplied as a build option. The platform has the 3022 option of excluding the BL33 image in the ``fip`` image by defining this flag 3023 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 3024 are used, this flag will be set to ``no`` automatically. 3025 3026Platform include paths 3027---------------------- 3028 3029Platforms are allowed to add more include paths to be passed to the compiler. 3030The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in 3031particular for the file ``platform_def.h``. 3032 3033Example: 3034 3035.. code:: c 3036 3037 PLAT_INCLUDES += -Iinclude/plat/myplat/include 3038 3039C Library 3040--------- 3041 3042To avoid subtle toolchain behavioral dependencies, the header files provided 3043by the compiler are not used. The software is built with the ``-nostdinc`` flag 3044to ensure no headers are included from the toolchain inadvertently. Instead the 3045required headers are included in the TF-A source tree. The library only 3046contains those C library definitions required by the local implementation. If 3047more functionality is required, the needed library functions will need to be 3048added to the local implementation. 3049 3050Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 3051been written specifically for TF-A. Some implementation files have been obtained 3052from `FreeBSD`_, others have been written specifically for TF-A as well. The 3053files can be found in ``include/lib/libc`` and ``lib/libc``. 3054 3055SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources 3056can be obtained from http://github.com/freebsd/freebsd. 3057 3058Storage abstraction layer 3059------------------------- 3060 3061In order to improve platform independence and portability a storage abstraction 3062layer is used to load data from non-volatile platform storage. Currently 3063storage access is only required by BL1 and BL2 phases and performed inside the 3064``load_image()`` function in ``bl_common.c``. 3065 3066.. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml 3067 3068It is mandatory to implement at least one storage driver. For the Arm 3069development platforms the Firmware Image Package (FIP) driver is provided as 3070the default means to load data from storage (see :ref:`firmware_design_fip`). 3071The storage layer is described in the header file 3072``include/drivers/io/io_storage.h``. The implementation of the common library is 3073in ``drivers/io/io_storage.c`` and the driver files are located in 3074``drivers/io/``. 3075 3076.. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml 3077 3078Each IO driver must provide ``io_dev_*`` structures, as described in 3079``drivers/io/io_driver.h``. These are returned via a mandatory registration 3080function that is called on platform initialization. The semi-hosting driver 3081implementation in ``io_semihosting.c`` can be used as an example. 3082 3083Each platform should register devices and their drivers via the storage 3084abstraction layer. These drivers then need to be initialized by bootloader 3085phases as required in their respective ``blx_platform_setup()`` functions. 3086 3087.. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml 3088 3089The storage abstraction layer provides mechanisms (``io_dev_init()``) to 3090initialize storage devices before IO operations are called. 3091 3092.. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml 3093 3094The basic operations supported by the layer 3095include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 3096Drivers do not have to implement all operations, but each platform must 3097provide at least one driver for a device capable of supporting generic 3098operations such as loading a bootloader image. 3099 3100The current implementation only allows for known images to be loaded by the 3101firmware. These images are specified by using their identifiers, as defined in 3102``include/plat/common/common_def.h`` (or a separate header file included from 3103there). The platform layer (``plat_get_image_source()``) then returns a reference 3104to a device and a driver-specific ``spec`` which will be understood by the driver 3105to allow access to the image data. 3106 3107The layer is designed in such a way that is it possible to chain drivers with 3108other drivers. For example, file-system drivers may be implemented on top of 3109physical block devices, both represented by IO devices with corresponding 3110drivers. In such a case, the file-system "binding" with the block device may 3111be deferred until the file-system device is initialised. 3112 3113The abstraction currently depends on structures being statically allocated 3114by the drivers and callers, as the system does not yet provide a means of 3115dynamically allocating memory. This may also have the affect of limiting the 3116amount of open resources per driver. 3117 3118-------------- 3119 3120*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.* 3121 3122.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 3123.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 3124.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 3125.. _FreeBSD: https://www.freebsd.org 3126.. _SCC: http://www.simple-cc.org/ 3127