xref: /aosp_15_r20/external/arm-trusted-firmware/docs/components/fconf/mpmm-bindings.rst (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1*54fd6939SJiyong ParkMaximum Power Mitigation Mechanism (MPMM) Bindings
2*54fd6939SJiyong Park==================================================
3*54fd6939SJiyong Park
4*54fd6939SJiyong Park|MPMM| support cannot be determined at runtime by the firmware. Instead, these
5*54fd6939SJiyong ParkDTB bindings allow the platform to communicate per-core support for |MPMM| via
6*54fd6939SJiyong Parkthe ``HW_CONFIG`` device tree blob.
7*54fd6939SJiyong Park
8*54fd6939SJiyong ParkBindings
9*54fd6939SJiyong Park^^^^^^^^
10*54fd6939SJiyong Park
11*54fd6939SJiyong Park.. contents::
12*54fd6939SJiyong Park    :local:
13*54fd6939SJiyong Park
14*54fd6939SJiyong Park``/cpus/cpus/cpu*`` node properties
15*54fd6939SJiyong Park"""""""""""""""""""""""""""""""""""
16*54fd6939SJiyong Park
17*54fd6939SJiyong ParkThe ``cpu`` node has been augmented to allow the platform to indicate support
18*54fd6939SJiyong Parkfor |MPMM| on a given core.
19*54fd6939SJiyong Park
20*54fd6939SJiyong Park+-------------------+-------+-------------+------------------------------------+
21*54fd6939SJiyong Park| Property name     | Usage | Value type  | Description                        |
22*54fd6939SJiyong Park+===================+=======+=============+====================================+
23*54fd6939SJiyong Park| ``supports-mpmm`` | O     | ``<empty>`` | If present, indicates that |MPMM|  |
24*54fd6939SJiyong Park|                   |       |             | is available on this core.         |
25*54fd6939SJiyong Park+-------------------+-------+-------------+------------------------------------+
26*54fd6939SJiyong Park
27*54fd6939SJiyong ParkExample
28*54fd6939SJiyong Park^^^^^^^
29*54fd6939SJiyong Park
30*54fd6939SJiyong ParkAn example system offering two cores, one with support for |MPMM| and one
31*54fd6939SJiyong Parkwithout, can be described as follows:
32*54fd6939SJiyong Park
33*54fd6939SJiyong Park.. code-block::
34*54fd6939SJiyong Park
35*54fd6939SJiyong Park    cpus {
36*54fd6939SJiyong Park        #address-cells = <2>;
37*54fd6939SJiyong Park        #size-cells = <0>;
38*54fd6939SJiyong Park
39*54fd6939SJiyong Park        cpu0@00000 {
40*54fd6939SJiyong Park            ...
41*54fd6939SJiyong Park
42*54fd6939SJiyong Park            supports-mpmm;
43*54fd6939SJiyong Park        };
44*54fd6939SJiyong Park
45*54fd6939SJiyong Park        cpu1@00100 {
46*54fd6939SJiyong Park            ...
47*54fd6939SJiyong Park        };
48*54fd6939SJiyong Park    }
49