1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <asm_macros.S> 8*54fd6939SJiyong Park#include <common/bl_common.h> 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park/* ----------------------------------------------------------------------------- 11*54fd6939SJiyong Park * Very simple stackless exception handlers used by BL2 and BL31 stages. 12*54fd6939SJiyong Park * BL31 uses them before stacks are setup. BL2 uses them throughout. 13*54fd6939SJiyong Park * ----------------------------------------------------------------------------- 14*54fd6939SJiyong Park */ 15*54fd6939SJiyong Park .globl early_exceptions 16*54fd6939SJiyong Park 17*54fd6939SJiyong Parkvector_base early_exceptions 18*54fd6939SJiyong Park 19*54fd6939SJiyong Park /* ----------------------------------------------------- 20*54fd6939SJiyong Park * Current EL with SP0 : 0x0 - 0x200 21*54fd6939SJiyong Park * ----------------------------------------------------- 22*54fd6939SJiyong Park */ 23*54fd6939SJiyong Parkvector_entry SynchronousExceptionSP0 24*54fd6939SJiyong Park mov x0, #SYNC_EXCEPTION_SP_EL0 25*54fd6939SJiyong Park bl plat_report_exception 26*54fd6939SJiyong Park no_ret plat_panic_handler 27*54fd6939SJiyong Parkend_vector_entry SynchronousExceptionSP0 28*54fd6939SJiyong Park 29*54fd6939SJiyong Parkvector_entry IrqSP0 30*54fd6939SJiyong Park mov x0, #IRQ_SP_EL0 31*54fd6939SJiyong Park bl plat_report_exception 32*54fd6939SJiyong Park no_ret plat_panic_handler 33*54fd6939SJiyong Parkend_vector_entry IrqSP0 34*54fd6939SJiyong Park 35*54fd6939SJiyong Parkvector_entry FiqSP0 36*54fd6939SJiyong Park mov x0, #FIQ_SP_EL0 37*54fd6939SJiyong Park bl plat_report_exception 38*54fd6939SJiyong Park no_ret plat_panic_handler 39*54fd6939SJiyong Parkend_vector_entry FiqSP0 40*54fd6939SJiyong Park 41*54fd6939SJiyong Parkvector_entry SErrorSP0 42*54fd6939SJiyong Park mov x0, #SERROR_SP_EL0 43*54fd6939SJiyong Park bl plat_report_exception 44*54fd6939SJiyong Park no_ret plat_panic_handler 45*54fd6939SJiyong Parkend_vector_entry SErrorSP0 46*54fd6939SJiyong Park 47*54fd6939SJiyong Park /* ----------------------------------------------------- 48*54fd6939SJiyong Park * Current EL with SPx: 0x200 - 0x400 49*54fd6939SJiyong Park * ----------------------------------------------------- 50*54fd6939SJiyong Park */ 51*54fd6939SJiyong Parkvector_entry SynchronousExceptionSPx 52*54fd6939SJiyong Park mov x0, #SYNC_EXCEPTION_SP_ELX 53*54fd6939SJiyong Park bl plat_report_exception 54*54fd6939SJiyong Park no_ret plat_panic_handler 55*54fd6939SJiyong Parkend_vector_entry SynchronousExceptionSPx 56*54fd6939SJiyong Park 57*54fd6939SJiyong Parkvector_entry IrqSPx 58*54fd6939SJiyong Park mov x0, #IRQ_SP_ELX 59*54fd6939SJiyong Park bl plat_report_exception 60*54fd6939SJiyong Park no_ret plat_panic_handler 61*54fd6939SJiyong Parkend_vector_entry IrqSPx 62*54fd6939SJiyong Park 63*54fd6939SJiyong Parkvector_entry FiqSPx 64*54fd6939SJiyong Park mov x0, #FIQ_SP_ELX 65*54fd6939SJiyong Park bl plat_report_exception 66*54fd6939SJiyong Park no_ret plat_panic_handler 67*54fd6939SJiyong Parkend_vector_entry FiqSPx 68*54fd6939SJiyong Park 69*54fd6939SJiyong Parkvector_entry SErrorSPx 70*54fd6939SJiyong Park mov x0, #SERROR_SP_ELX 71*54fd6939SJiyong Park bl plat_report_exception 72*54fd6939SJiyong Park no_ret plat_panic_handler 73*54fd6939SJiyong Parkend_vector_entry SErrorSPx 74*54fd6939SJiyong Park 75*54fd6939SJiyong Park /* ----------------------------------------------------- 76*54fd6939SJiyong Park * Lower EL using AArch64 : 0x400 - 0x600 77*54fd6939SJiyong Park * ----------------------------------------------------- 78*54fd6939SJiyong Park */ 79*54fd6939SJiyong Parkvector_entry SynchronousExceptionA64 80*54fd6939SJiyong Park mov x0, #SYNC_EXCEPTION_AARCH64 81*54fd6939SJiyong Park bl plat_report_exception 82*54fd6939SJiyong Park no_ret plat_panic_handler 83*54fd6939SJiyong Parkend_vector_entry SynchronousExceptionA64 84*54fd6939SJiyong Park 85*54fd6939SJiyong Parkvector_entry IrqA64 86*54fd6939SJiyong Park mov x0, #IRQ_AARCH64 87*54fd6939SJiyong Park bl plat_report_exception 88*54fd6939SJiyong Park no_ret plat_panic_handler 89*54fd6939SJiyong Parkend_vector_entry IrqA64 90*54fd6939SJiyong Park 91*54fd6939SJiyong Parkvector_entry FiqA64 92*54fd6939SJiyong Park mov x0, #FIQ_AARCH64 93*54fd6939SJiyong Park bl plat_report_exception 94*54fd6939SJiyong Park no_ret plat_panic_handler 95*54fd6939SJiyong Parkend_vector_entry FiqA64 96*54fd6939SJiyong Park 97*54fd6939SJiyong Parkvector_entry SErrorA64 98*54fd6939SJiyong Park mov x0, #SERROR_AARCH64 99*54fd6939SJiyong Park bl plat_report_exception 100*54fd6939SJiyong Park no_ret plat_panic_handler 101*54fd6939SJiyong Parkend_vector_entry SErrorA64 102*54fd6939SJiyong Park 103*54fd6939SJiyong Park /* ----------------------------------------------------- 104*54fd6939SJiyong Park * Lower EL using AArch32 : 0x600 - 0x800 105*54fd6939SJiyong Park * ----------------------------------------------------- 106*54fd6939SJiyong Park */ 107*54fd6939SJiyong Parkvector_entry SynchronousExceptionA32 108*54fd6939SJiyong Park mov x0, #SYNC_EXCEPTION_AARCH32 109*54fd6939SJiyong Park bl plat_report_exception 110*54fd6939SJiyong Park no_ret plat_panic_handler 111*54fd6939SJiyong Parkend_vector_entry SynchronousExceptionA32 112*54fd6939SJiyong Park 113*54fd6939SJiyong Parkvector_entry IrqA32 114*54fd6939SJiyong Park mov x0, #IRQ_AARCH32 115*54fd6939SJiyong Park bl plat_report_exception 116*54fd6939SJiyong Park no_ret plat_panic_handler 117*54fd6939SJiyong Parkend_vector_entry IrqA32 118*54fd6939SJiyong Park 119*54fd6939SJiyong Parkvector_entry FiqA32 120*54fd6939SJiyong Park mov x0, #FIQ_AARCH32 121*54fd6939SJiyong Park bl plat_report_exception 122*54fd6939SJiyong Park no_ret plat_panic_handler 123*54fd6939SJiyong Parkend_vector_entry FiqA32 124*54fd6939SJiyong Park 125*54fd6939SJiyong Parkvector_entry SErrorA32 126*54fd6939SJiyong Park mov x0, #SERROR_AARCH32 127*54fd6939SJiyong Park bl plat_report_exception 128*54fd6939SJiyong Park no_ret plat_panic_handler 129*54fd6939SJiyong Parkend_vector_entry SErrorA32 130