1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <arch.h> 8*54fd6939SJiyong Park#include <asm_macros.S> 9*54fd6939SJiyong Park#include <bl32/tsp/tsp.h> 10*54fd6939SJiyong Park#include <common/bl_common.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /* ---------------------------------------------------- 13*54fd6939SJiyong Park * The caller-saved registers x0-x18 and LR are saved 14*54fd6939SJiyong Park * here. 15*54fd6939SJiyong Park * ---------------------------------------------------- 16*54fd6939SJiyong Park */ 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park#define SCRATCH_REG_SIZE #(20 * 8) 19*54fd6939SJiyong Park 20*54fd6939SJiyong Park .macro save_caller_regs_and_lr 21*54fd6939SJiyong Park sub sp, sp, SCRATCH_REG_SIZE 22*54fd6939SJiyong Park stp x0, x1, [sp] 23*54fd6939SJiyong Park stp x2, x3, [sp, #0x10] 24*54fd6939SJiyong Park stp x4, x5, [sp, #0x20] 25*54fd6939SJiyong Park stp x6, x7, [sp, #0x30] 26*54fd6939SJiyong Park stp x8, x9, [sp, #0x40] 27*54fd6939SJiyong Park stp x10, x11, [sp, #0x50] 28*54fd6939SJiyong Park stp x12, x13, [sp, #0x60] 29*54fd6939SJiyong Park stp x14, x15, [sp, #0x70] 30*54fd6939SJiyong Park stp x16, x17, [sp, #0x80] 31*54fd6939SJiyong Park stp x18, x30, [sp, #0x90] 32*54fd6939SJiyong Park .endm 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park .macro restore_caller_regs_and_lr 35*54fd6939SJiyong Park ldp x0, x1, [sp] 36*54fd6939SJiyong Park ldp x2, x3, [sp, #0x10] 37*54fd6939SJiyong Park ldp x4, x5, [sp, #0x20] 38*54fd6939SJiyong Park ldp x6, x7, [sp, #0x30] 39*54fd6939SJiyong Park ldp x8, x9, [sp, #0x40] 40*54fd6939SJiyong Park ldp x10, x11, [sp, #0x50] 41*54fd6939SJiyong Park ldp x12, x13, [sp, #0x60] 42*54fd6939SJiyong Park ldp x14, x15, [sp, #0x70] 43*54fd6939SJiyong Park ldp x16, x17, [sp, #0x80] 44*54fd6939SJiyong Park ldp x18, x30, [sp, #0x90] 45*54fd6939SJiyong Park add sp, sp, SCRATCH_REG_SIZE 46*54fd6939SJiyong Park .endm 47*54fd6939SJiyong Park 48*54fd6939SJiyong Park /* ---------------------------------------------------- 49*54fd6939SJiyong Park * Common TSP interrupt handling routine 50*54fd6939SJiyong Park * ---------------------------------------------------- 51*54fd6939SJiyong Park */ 52*54fd6939SJiyong Park .macro handle_tsp_interrupt label 53*54fd6939SJiyong Park /* Enable the SError interrupt */ 54*54fd6939SJiyong Park msr daifclr, #DAIF_ABT_BIT 55*54fd6939SJiyong Park 56*54fd6939SJiyong Park save_caller_regs_and_lr 57*54fd6939SJiyong Park bl tsp_common_int_handler 58*54fd6939SJiyong Park cbz x0, interrupt_exit_\label 59*54fd6939SJiyong Park 60*54fd6939SJiyong Park /* 61*54fd6939SJiyong Park * This interrupt was not targetted to S-EL1 so send it to 62*54fd6939SJiyong Park * the monitor and wait for execution to resume. 63*54fd6939SJiyong Park */ 64*54fd6939SJiyong Park smc #0 65*54fd6939SJiyong Parkinterrupt_exit_\label: 66*54fd6939SJiyong Park restore_caller_regs_and_lr 67*54fd6939SJiyong Park exception_return 68*54fd6939SJiyong Park .endm 69*54fd6939SJiyong Park 70*54fd6939SJiyong Park .globl tsp_exceptions 71*54fd6939SJiyong Park 72*54fd6939SJiyong Park /* ----------------------------------------------------- 73*54fd6939SJiyong Park * TSP exception handlers. 74*54fd6939SJiyong Park * ----------------------------------------------------- 75*54fd6939SJiyong Park */ 76*54fd6939SJiyong Parkvector_base tsp_exceptions 77*54fd6939SJiyong Park /* ----------------------------------------------------- 78*54fd6939SJiyong Park * Current EL with _sp_el0 : 0x0 - 0x200. No exceptions 79*54fd6939SJiyong Park * are expected and treated as irrecoverable errors. 80*54fd6939SJiyong Park * ----------------------------------------------------- 81*54fd6939SJiyong Park */ 82*54fd6939SJiyong Parkvector_entry sync_exception_sp_el0 83*54fd6939SJiyong Park b plat_panic_handler 84*54fd6939SJiyong Parkend_vector_entry sync_exception_sp_el0 85*54fd6939SJiyong Park 86*54fd6939SJiyong Parkvector_entry irq_sp_el0 87*54fd6939SJiyong Park b plat_panic_handler 88*54fd6939SJiyong Parkend_vector_entry irq_sp_el0 89*54fd6939SJiyong Park 90*54fd6939SJiyong Parkvector_entry fiq_sp_el0 91*54fd6939SJiyong Park b plat_panic_handler 92*54fd6939SJiyong Parkend_vector_entry fiq_sp_el0 93*54fd6939SJiyong Park 94*54fd6939SJiyong Parkvector_entry serror_sp_el0 95*54fd6939SJiyong Park b plat_panic_handler 96*54fd6939SJiyong Parkend_vector_entry serror_sp_el0 97*54fd6939SJiyong Park 98*54fd6939SJiyong Park 99*54fd6939SJiyong Park /* ----------------------------------------------------- 100*54fd6939SJiyong Park * Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs 101*54fd6939SJiyong Park * are expected and handled 102*54fd6939SJiyong Park * ----------------------------------------------------- 103*54fd6939SJiyong Park */ 104*54fd6939SJiyong Parkvector_entry sync_exception_sp_elx 105*54fd6939SJiyong Park b plat_panic_handler 106*54fd6939SJiyong Parkend_vector_entry sync_exception_sp_elx 107*54fd6939SJiyong Park 108*54fd6939SJiyong Parkvector_entry irq_sp_elx 109*54fd6939SJiyong Park handle_tsp_interrupt irq_sp_elx 110*54fd6939SJiyong Parkend_vector_entry irq_sp_elx 111*54fd6939SJiyong Park 112*54fd6939SJiyong Parkvector_entry fiq_sp_elx 113*54fd6939SJiyong Park handle_tsp_interrupt fiq_sp_elx 114*54fd6939SJiyong Parkend_vector_entry fiq_sp_elx 115*54fd6939SJiyong Park 116*54fd6939SJiyong Parkvector_entry serror_sp_elx 117*54fd6939SJiyong Park b plat_panic_handler 118*54fd6939SJiyong Parkend_vector_entry serror_sp_elx 119*54fd6939SJiyong Park 120*54fd6939SJiyong Park 121*54fd6939SJiyong Park /* ----------------------------------------------------- 122*54fd6939SJiyong Park * Lower EL using AArch64 : 0x400 - 0x600. No exceptions 123*54fd6939SJiyong Park * are handled since TSP does not implement a lower EL 124*54fd6939SJiyong Park * ----------------------------------------------------- 125*54fd6939SJiyong Park */ 126*54fd6939SJiyong Parkvector_entry sync_exception_aarch64 127*54fd6939SJiyong Park b plat_panic_handler 128*54fd6939SJiyong Parkend_vector_entry sync_exception_aarch64 129*54fd6939SJiyong Park 130*54fd6939SJiyong Parkvector_entry irq_aarch64 131*54fd6939SJiyong Park b plat_panic_handler 132*54fd6939SJiyong Parkend_vector_entry irq_aarch64 133*54fd6939SJiyong Park 134*54fd6939SJiyong Parkvector_entry fiq_aarch64 135*54fd6939SJiyong Park b plat_panic_handler 136*54fd6939SJiyong Parkend_vector_entry fiq_aarch64 137*54fd6939SJiyong Park 138*54fd6939SJiyong Parkvector_entry serror_aarch64 139*54fd6939SJiyong Park b plat_panic_handler 140*54fd6939SJiyong Parkend_vector_entry serror_aarch64 141*54fd6939SJiyong Park 142*54fd6939SJiyong Park 143*54fd6939SJiyong Park /* ----------------------------------------------------- 144*54fd6939SJiyong Park * Lower EL using AArch32 : 0x600 - 0x800. No exceptions 145*54fd6939SJiyong Park * handled since the TSP does not implement a lower EL. 146*54fd6939SJiyong Park * ----------------------------------------------------- 147*54fd6939SJiyong Park */ 148*54fd6939SJiyong Parkvector_entry sync_exception_aarch32 149*54fd6939SJiyong Park b plat_panic_handler 150*54fd6939SJiyong Parkend_vector_entry sync_exception_aarch32 151*54fd6939SJiyong Park 152*54fd6939SJiyong Parkvector_entry irq_aarch32 153*54fd6939SJiyong Park b plat_panic_handler 154*54fd6939SJiyong Parkend_vector_entry irq_aarch32 155*54fd6939SJiyong Park 156*54fd6939SJiyong Parkvector_entry fiq_aarch32 157*54fd6939SJiyong Park b plat_panic_handler 158*54fd6939SJiyong Parkend_vector_entry fiq_aarch32 159*54fd6939SJiyong Park 160*54fd6939SJiyong Parkvector_entry serror_aarch32 161*54fd6939SJiyong Park b plat_panic_handler 162*54fd6939SJiyong Parkend_vector_entry serror_aarch32 163