xref: /aosp_15_r20/external/arm-trusted-firmware/bl2u/bl2u.ld.S (revision 54fd6939e177f8ff529b10183254802c76df6d08) 
1*54fd6939SJiyong Park/*
2*54fd6939SJiyong Park * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park#include <platform_def.h>
8*54fd6939SJiyong Park
9*54fd6939SJiyong Park#include <common/bl_common.ld.h>
10*54fd6939SJiyong Park#include <lib/xlat_tables/xlat_tables_defs.h>
11*54fd6939SJiyong Park
12*54fd6939SJiyong ParkOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
13*54fd6939SJiyong ParkOUTPUT_ARCH(PLATFORM_LINKER_ARCH)
14*54fd6939SJiyong ParkENTRY(bl2u_entrypoint)
15*54fd6939SJiyong Park
16*54fd6939SJiyong ParkMEMORY {
17*54fd6939SJiyong Park    RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
18*54fd6939SJiyong Park}
19*54fd6939SJiyong Park
20*54fd6939SJiyong Park
21*54fd6939SJiyong ParkSECTIONS
22*54fd6939SJiyong Park{
23*54fd6939SJiyong Park    . = BL2U_BASE;
24*54fd6939SJiyong Park    ASSERT(. == ALIGN(PAGE_SIZE),
25*54fd6939SJiyong Park           "BL2U_BASE address is not aligned on a page boundary.")
26*54fd6939SJiyong Park
27*54fd6939SJiyong Park#if SEPARATE_CODE_AND_RODATA
28*54fd6939SJiyong Park    .text . : {
29*54fd6939SJiyong Park        __TEXT_START__ = .;
30*54fd6939SJiyong Park        *bl2u_entrypoint.o(.text*)
31*54fd6939SJiyong Park        *(SORT_BY_ALIGNMENT(.text*))
32*54fd6939SJiyong Park        *(.vectors)
33*54fd6939SJiyong Park        . = ALIGN(PAGE_SIZE);
34*54fd6939SJiyong Park        __TEXT_END__ = .;
35*54fd6939SJiyong Park     } >RAM
36*54fd6939SJiyong Park
37*54fd6939SJiyong Park     /* .ARM.extab and .ARM.exidx are only added because Clang need them */
38*54fd6939SJiyong Park     .ARM.extab . : {
39*54fd6939SJiyong Park        *(.ARM.extab* .gnu.linkonce.armextab.*)
40*54fd6939SJiyong Park     } >RAM
41*54fd6939SJiyong Park
42*54fd6939SJiyong Park     .ARM.exidx . : {
43*54fd6939SJiyong Park        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
44*54fd6939SJiyong Park     } >RAM
45*54fd6939SJiyong Park
46*54fd6939SJiyong Park    .rodata . : {
47*54fd6939SJiyong Park        __RODATA_START__ = .;
48*54fd6939SJiyong Park        *(SORT_BY_ALIGNMENT(.rodata*))
49*54fd6939SJiyong Park
50*54fd6939SJiyong Park	RODATA_COMMON
51*54fd6939SJiyong Park
52*54fd6939SJiyong Park        . = ALIGN(PAGE_SIZE);
53*54fd6939SJiyong Park        __RODATA_END__ = .;
54*54fd6939SJiyong Park    } >RAM
55*54fd6939SJiyong Park#else
56*54fd6939SJiyong Park    ro . : {
57*54fd6939SJiyong Park        __RO_START__ = .;
58*54fd6939SJiyong Park        *bl2u_entrypoint.o(.text*)
59*54fd6939SJiyong Park        *(SORT_BY_ALIGNMENT(.text*))
60*54fd6939SJiyong Park        *(SORT_BY_ALIGNMENT(.rodata*))
61*54fd6939SJiyong Park
62*54fd6939SJiyong Park	RODATA_COMMON
63*54fd6939SJiyong Park
64*54fd6939SJiyong Park        *(.vectors)
65*54fd6939SJiyong Park        __RO_END_UNALIGNED__ = .;
66*54fd6939SJiyong Park        /*
67*54fd6939SJiyong Park         * Memory page(s) mapped to this section will be marked as
68*54fd6939SJiyong Park         * read-only, executable.  No RW data from the next section must
69*54fd6939SJiyong Park         * creep in.  Ensure the rest of the current memory page is unused.
70*54fd6939SJiyong Park         */
71*54fd6939SJiyong Park        . = ALIGN(PAGE_SIZE);
72*54fd6939SJiyong Park        __RO_END__ = .;
73*54fd6939SJiyong Park    } >RAM
74*54fd6939SJiyong Park#endif
75*54fd6939SJiyong Park
76*54fd6939SJiyong Park    /*
77*54fd6939SJiyong Park     * Define a linker symbol to mark start of the RW memory area for this
78*54fd6939SJiyong Park     * image.
79*54fd6939SJiyong Park     */
80*54fd6939SJiyong Park    __RW_START__ = . ;
81*54fd6939SJiyong Park
82*54fd6939SJiyong Park    DATA_SECTION >RAM
83*54fd6939SJiyong Park    STACK_SECTION >RAM
84*54fd6939SJiyong Park    BSS_SECTION >RAM
85*54fd6939SJiyong Park    XLAT_TABLE_SECTION >RAM
86*54fd6939SJiyong Park
87*54fd6939SJiyong Park#if USE_COHERENT_MEM
88*54fd6939SJiyong Park    /*
89*54fd6939SJiyong Park     * The base address of the coherent memory section must be page-aligned (4K)
90*54fd6939SJiyong Park     * to guarantee that the coherent data are stored on their own pages and
91*54fd6939SJiyong Park     * are not mixed with normal data.  This is required to set up the correct
92*54fd6939SJiyong Park     * memory attributes for the coherent data page tables.
93*54fd6939SJiyong Park     */
94*54fd6939SJiyong Park    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
95*54fd6939SJiyong Park        __COHERENT_RAM_START__ = .;
96*54fd6939SJiyong Park        *(tzfw_coherent_mem)
97*54fd6939SJiyong Park        __COHERENT_RAM_END_UNALIGNED__ = .;
98*54fd6939SJiyong Park        /*
99*54fd6939SJiyong Park         * Memory page(s) mapped to this section will be marked
100*54fd6939SJiyong Park         * as device memory.  No other unexpected data must creep in.
101*54fd6939SJiyong Park         * Ensure the rest of the current memory page is unused.
102*54fd6939SJiyong Park         */
103*54fd6939SJiyong Park        . = ALIGN(PAGE_SIZE);
104*54fd6939SJiyong Park        __COHERENT_RAM_END__ = .;
105*54fd6939SJiyong Park    } >RAM
106*54fd6939SJiyong Park#endif
107*54fd6939SJiyong Park
108*54fd6939SJiyong Park    /*
109*54fd6939SJiyong Park     * Define a linker symbol to mark end of the RW memory area for this
110*54fd6939SJiyong Park     * image.
111*54fd6939SJiyong Park     */
112*54fd6939SJiyong Park    __RW_END__ = .;
113*54fd6939SJiyong Park    __BL2U_END__ = .;
114*54fd6939SJiyong Park
115*54fd6939SJiyong Park    __BSS_SIZE__ = SIZEOF(.bss);
116*54fd6939SJiyong Park
117*54fd6939SJiyong Park    ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
118*54fd6939SJiyong Park}
119