1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <arch.h> 8*54fd6939SJiyong Park#include <asm_macros.S> 9*54fd6939SJiyong Park#include <common/bl_common.h> 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park .globl bl2_entrypoint 13*54fd6939SJiyong Park 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park 16*54fd6939SJiyong Parkfunc bl2_entrypoint 17*54fd6939SJiyong Park /*--------------------------------------------- 18*54fd6939SJiyong Park * Save arguments x0 - x3 from BL1 for future 19*54fd6939SJiyong Park * use. 20*54fd6939SJiyong Park * --------------------------------------------- 21*54fd6939SJiyong Park */ 22*54fd6939SJiyong Park mov x20, x0 23*54fd6939SJiyong Park mov x21, x1 24*54fd6939SJiyong Park mov x22, x2 25*54fd6939SJiyong Park mov x23, x3 26*54fd6939SJiyong Park 27*54fd6939SJiyong Park /* --------------------------------------------- 28*54fd6939SJiyong Park * Set the exception vector to something sane. 29*54fd6939SJiyong Park * --------------------------------------------- 30*54fd6939SJiyong Park */ 31*54fd6939SJiyong Park adr x0, early_exceptions 32*54fd6939SJiyong Park msr vbar_el1, x0 33*54fd6939SJiyong Park isb 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park /* --------------------------------------------- 36*54fd6939SJiyong Park * Enable the SError interrupt now that the 37*54fd6939SJiyong Park * exception vectors have been setup. 38*54fd6939SJiyong Park * --------------------------------------------- 39*54fd6939SJiyong Park */ 40*54fd6939SJiyong Park msr daifclr, #DAIF_ABT_BIT 41*54fd6939SJiyong Park 42*54fd6939SJiyong Park /* --------------------------------------------- 43*54fd6939SJiyong Park * Enable the instruction cache, stack pointer 44*54fd6939SJiyong Park * and data access alignment checks and disable 45*54fd6939SJiyong Park * speculative loads. 46*54fd6939SJiyong Park * --------------------------------------------- 47*54fd6939SJiyong Park */ 48*54fd6939SJiyong Park mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 49*54fd6939SJiyong Park mrs x0, sctlr_el1 50*54fd6939SJiyong Park orr x0, x0, x1 51*54fd6939SJiyong Park bic x0, x0, #SCTLR_DSSBS_BIT 52*54fd6939SJiyong Park msr sctlr_el1, x0 53*54fd6939SJiyong Park isb 54*54fd6939SJiyong Park 55*54fd6939SJiyong Park /* --------------------------------------------- 56*54fd6939SJiyong Park * Invalidate the RW memory used by the BL2 57*54fd6939SJiyong Park * image. This includes the data and NOBITS 58*54fd6939SJiyong Park * sections. This is done to safeguard against 59*54fd6939SJiyong Park * possible corruption of this memory by dirty 60*54fd6939SJiyong Park * cache lines in a system cache as a result of 61*54fd6939SJiyong Park * use by an earlier boot loader stage. 62*54fd6939SJiyong Park * --------------------------------------------- 63*54fd6939SJiyong Park */ 64*54fd6939SJiyong Park adr x0, __RW_START__ 65*54fd6939SJiyong Park adr x1, __RW_END__ 66*54fd6939SJiyong Park sub x1, x1, x0 67*54fd6939SJiyong Park bl inv_dcache_range 68*54fd6939SJiyong Park 69*54fd6939SJiyong Park /* --------------------------------------------- 70*54fd6939SJiyong Park * Zero out NOBITS sections. There are 2 of them: 71*54fd6939SJiyong Park * - the .bss section; 72*54fd6939SJiyong Park * - the coherent memory section. 73*54fd6939SJiyong Park * --------------------------------------------- 74*54fd6939SJiyong Park */ 75*54fd6939SJiyong Park adrp x0, __BSS_START__ 76*54fd6939SJiyong Park add x0, x0, :lo12:__BSS_START__ 77*54fd6939SJiyong Park adrp x1, __BSS_END__ 78*54fd6939SJiyong Park add x1, x1, :lo12:__BSS_END__ 79*54fd6939SJiyong Park sub x1, x1, x0 80*54fd6939SJiyong Park bl zeromem 81*54fd6939SJiyong Park 82*54fd6939SJiyong Park#if USE_COHERENT_MEM 83*54fd6939SJiyong Park adrp x0, __COHERENT_RAM_START__ 84*54fd6939SJiyong Park add x0, x0, :lo12:__COHERENT_RAM_START__ 85*54fd6939SJiyong Park adrp x1, __COHERENT_RAM_END_UNALIGNED__ 86*54fd6939SJiyong Park add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__ 87*54fd6939SJiyong Park sub x1, x1, x0 88*54fd6939SJiyong Park bl zeromem 89*54fd6939SJiyong Park#endif 90*54fd6939SJiyong Park 91*54fd6939SJiyong Park /* -------------------------------------------- 92*54fd6939SJiyong Park * Allocate a stack whose memory will be marked 93*54fd6939SJiyong Park * as Normal-IS-WBWA when the MMU is enabled. 94*54fd6939SJiyong Park * There is no risk of reading stale stack 95*54fd6939SJiyong Park * memory after enabling the MMU as only the 96*54fd6939SJiyong Park * primary cpu is running at the moment. 97*54fd6939SJiyong Park * -------------------------------------------- 98*54fd6939SJiyong Park */ 99*54fd6939SJiyong Park bl plat_set_my_stack 100*54fd6939SJiyong Park 101*54fd6939SJiyong Park /* --------------------------------------------- 102*54fd6939SJiyong Park * Initialize the stack protector canary before 103*54fd6939SJiyong Park * any C code is called. 104*54fd6939SJiyong Park * --------------------------------------------- 105*54fd6939SJiyong Park */ 106*54fd6939SJiyong Park#if STACK_PROTECTOR_ENABLED 107*54fd6939SJiyong Park bl update_stack_protector_canary 108*54fd6939SJiyong Park#endif 109*54fd6939SJiyong Park 110*54fd6939SJiyong Park /* --------------------------------------------- 111*54fd6939SJiyong Park * Perform BL2 setup 112*54fd6939SJiyong Park * --------------------------------------------- 113*54fd6939SJiyong Park */ 114*54fd6939SJiyong Park mov x0, x20 115*54fd6939SJiyong Park mov x1, x21 116*54fd6939SJiyong Park mov x2, x22 117*54fd6939SJiyong Park mov x3, x23 118*54fd6939SJiyong Park bl bl2_setup 119*54fd6939SJiyong Park 120*54fd6939SJiyong Park#if ENABLE_PAUTH 121*54fd6939SJiyong Park /* --------------------------------------------- 122*54fd6939SJiyong Park * Program APIAKey_EL1 123*54fd6939SJiyong Park * and enable pointer authentication. 124*54fd6939SJiyong Park * --------------------------------------------- 125*54fd6939SJiyong Park */ 126*54fd6939SJiyong Park bl pauth_init_enable_el1 127*54fd6939SJiyong Park#endif /* ENABLE_PAUTH */ 128*54fd6939SJiyong Park 129*54fd6939SJiyong Park /* --------------------------------------------- 130*54fd6939SJiyong Park * Jump to main function. 131*54fd6939SJiyong Park * --------------------------------------------- 132*54fd6939SJiyong Park */ 133*54fd6939SJiyong Park bl bl2_main 134*54fd6939SJiyong Park 135*54fd6939SJiyong Park /* --------------------------------------------- 136*54fd6939SJiyong Park * Should never reach this point. 137*54fd6939SJiyong Park * --------------------------------------------- 138*54fd6939SJiyong Park */ 139*54fd6939SJiyong Park no_ret plat_panic_handler 140*54fd6939SJiyong Park 141*54fd6939SJiyong Parkendfunc bl2_entrypoint 142