1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <arch.h> 8*54fd6939SJiyong Park#include <asm_macros.S> 9*54fd6939SJiyong Park#include <bl1/bl1.h> 10*54fd6939SJiyong Park#include <common/bl_common.h> 11*54fd6939SJiyong Park#include <context.h> 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park/* ----------------------------------------------------------------------------- 14*54fd6939SJiyong Park * Very simple stackless exception handlers used by BL1. 15*54fd6939SJiyong Park * ----------------------------------------------------------------------------- 16*54fd6939SJiyong Park */ 17*54fd6939SJiyong Park .globl bl1_exceptions 18*54fd6939SJiyong Park 19*54fd6939SJiyong Parkvector_base bl1_exceptions 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park /* ----------------------------------------------------- 22*54fd6939SJiyong Park * Current EL with SP0 : 0x0 - 0x200 23*54fd6939SJiyong Park * ----------------------------------------------------- 24*54fd6939SJiyong Park */ 25*54fd6939SJiyong Parkvector_entry SynchronousExceptionSP0 26*54fd6939SJiyong Park mov x0, #SYNC_EXCEPTION_SP_EL0 27*54fd6939SJiyong Park bl plat_report_exception 28*54fd6939SJiyong Park no_ret plat_panic_handler 29*54fd6939SJiyong Parkend_vector_entry SynchronousExceptionSP0 30*54fd6939SJiyong Park 31*54fd6939SJiyong Parkvector_entry IrqSP0 32*54fd6939SJiyong Park mov x0, #IRQ_SP_EL0 33*54fd6939SJiyong Park bl plat_report_exception 34*54fd6939SJiyong Park no_ret plat_panic_handler 35*54fd6939SJiyong Parkend_vector_entry IrqSP0 36*54fd6939SJiyong Park 37*54fd6939SJiyong Parkvector_entry FiqSP0 38*54fd6939SJiyong Park mov x0, #FIQ_SP_EL0 39*54fd6939SJiyong Park bl plat_report_exception 40*54fd6939SJiyong Park no_ret plat_panic_handler 41*54fd6939SJiyong Parkend_vector_entry FiqSP0 42*54fd6939SJiyong Park 43*54fd6939SJiyong Parkvector_entry SErrorSP0 44*54fd6939SJiyong Park mov x0, #SERROR_SP_EL0 45*54fd6939SJiyong Park bl plat_report_exception 46*54fd6939SJiyong Park no_ret plat_panic_handler 47*54fd6939SJiyong Parkend_vector_entry SErrorSP0 48*54fd6939SJiyong Park 49*54fd6939SJiyong Park /* ----------------------------------------------------- 50*54fd6939SJiyong Park * Current EL with SPx: 0x200 - 0x400 51*54fd6939SJiyong Park * ----------------------------------------------------- 52*54fd6939SJiyong Park */ 53*54fd6939SJiyong Parkvector_entry SynchronousExceptionSPx 54*54fd6939SJiyong Park mov x0, #SYNC_EXCEPTION_SP_ELX 55*54fd6939SJiyong Park bl plat_report_exception 56*54fd6939SJiyong Park no_ret plat_panic_handler 57*54fd6939SJiyong Parkend_vector_entry SynchronousExceptionSPx 58*54fd6939SJiyong Park 59*54fd6939SJiyong Parkvector_entry IrqSPx 60*54fd6939SJiyong Park mov x0, #IRQ_SP_ELX 61*54fd6939SJiyong Park bl plat_report_exception 62*54fd6939SJiyong Park no_ret plat_panic_handler 63*54fd6939SJiyong Parkend_vector_entry IrqSPx 64*54fd6939SJiyong Park 65*54fd6939SJiyong Parkvector_entry FiqSPx 66*54fd6939SJiyong Park mov x0, #FIQ_SP_ELX 67*54fd6939SJiyong Park bl plat_report_exception 68*54fd6939SJiyong Park no_ret plat_panic_handler 69*54fd6939SJiyong Parkend_vector_entry FiqSPx 70*54fd6939SJiyong Park 71*54fd6939SJiyong Parkvector_entry SErrorSPx 72*54fd6939SJiyong Park mov x0, #SERROR_SP_ELX 73*54fd6939SJiyong Park bl plat_report_exception 74*54fd6939SJiyong Park no_ret plat_panic_handler 75*54fd6939SJiyong Parkend_vector_entry SErrorSPx 76*54fd6939SJiyong Park 77*54fd6939SJiyong Park /* ----------------------------------------------------- 78*54fd6939SJiyong Park * Lower EL using AArch64 : 0x400 - 0x600 79*54fd6939SJiyong Park * ----------------------------------------------------- 80*54fd6939SJiyong Park */ 81*54fd6939SJiyong Parkvector_entry SynchronousExceptionA64 82*54fd6939SJiyong Park /* Enable the SError interrupt */ 83*54fd6939SJiyong Park msr daifclr, #DAIF_ABT_BIT 84*54fd6939SJiyong Park 85*54fd6939SJiyong Park str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 86*54fd6939SJiyong Park 87*54fd6939SJiyong Park /* Expect only SMC exceptions */ 88*54fd6939SJiyong Park mrs x30, esr_el3 89*54fd6939SJiyong Park ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 90*54fd6939SJiyong Park cmp x30, #EC_AARCH64_SMC 91*54fd6939SJiyong Park b.ne unexpected_sync_exception 92*54fd6939SJiyong Park 93*54fd6939SJiyong Park b smc_handler64 94*54fd6939SJiyong Parkend_vector_entry SynchronousExceptionA64 95*54fd6939SJiyong Park 96*54fd6939SJiyong Parkvector_entry IrqA64 97*54fd6939SJiyong Park mov x0, #IRQ_AARCH64 98*54fd6939SJiyong Park bl plat_report_exception 99*54fd6939SJiyong Park no_ret plat_panic_handler 100*54fd6939SJiyong Parkend_vector_entry IrqA64 101*54fd6939SJiyong Park 102*54fd6939SJiyong Parkvector_entry FiqA64 103*54fd6939SJiyong Park mov x0, #FIQ_AARCH64 104*54fd6939SJiyong Park bl plat_report_exception 105*54fd6939SJiyong Park no_ret plat_panic_handler 106*54fd6939SJiyong Parkend_vector_entry FiqA64 107*54fd6939SJiyong Park 108*54fd6939SJiyong Parkvector_entry SErrorA64 109*54fd6939SJiyong Park mov x0, #SERROR_AARCH64 110*54fd6939SJiyong Park bl plat_report_exception 111*54fd6939SJiyong Park no_ret plat_panic_handler 112*54fd6939SJiyong Parkend_vector_entry SErrorA64 113*54fd6939SJiyong Park 114*54fd6939SJiyong Park /* ----------------------------------------------------- 115*54fd6939SJiyong Park * Lower EL using AArch32 : 0x600 - 0x800 116*54fd6939SJiyong Park * ----------------------------------------------------- 117*54fd6939SJiyong Park */ 118*54fd6939SJiyong Parkvector_entry SynchronousExceptionA32 119*54fd6939SJiyong Park mov x0, #SYNC_EXCEPTION_AARCH32 120*54fd6939SJiyong Park bl plat_report_exception 121*54fd6939SJiyong Park no_ret plat_panic_handler 122*54fd6939SJiyong Parkend_vector_entry SynchronousExceptionA32 123*54fd6939SJiyong Park 124*54fd6939SJiyong Parkvector_entry IrqA32 125*54fd6939SJiyong Park mov x0, #IRQ_AARCH32 126*54fd6939SJiyong Park bl plat_report_exception 127*54fd6939SJiyong Park no_ret plat_panic_handler 128*54fd6939SJiyong Parkend_vector_entry IrqA32 129*54fd6939SJiyong Park 130*54fd6939SJiyong Parkvector_entry FiqA32 131*54fd6939SJiyong Park mov x0, #FIQ_AARCH32 132*54fd6939SJiyong Park bl plat_report_exception 133*54fd6939SJiyong Park no_ret plat_panic_handler 134*54fd6939SJiyong Parkend_vector_entry FiqA32 135*54fd6939SJiyong Park 136*54fd6939SJiyong Parkvector_entry SErrorA32 137*54fd6939SJiyong Park mov x0, #SERROR_AARCH32 138*54fd6939SJiyong Park bl plat_report_exception 139*54fd6939SJiyong Park no_ret plat_panic_handler 140*54fd6939SJiyong Parkend_vector_entry SErrorA32 141*54fd6939SJiyong Park 142*54fd6939SJiyong Park 143*54fd6939SJiyong Parkfunc smc_handler64 144*54fd6939SJiyong Park 145*54fd6939SJiyong Park /* ---------------------------------------------- 146*54fd6939SJiyong Park * Detect if this is a RUN_IMAGE or other SMC. 147*54fd6939SJiyong Park * ---------------------------------------------- 148*54fd6939SJiyong Park */ 149*54fd6939SJiyong Park mov x30, #BL1_SMC_RUN_IMAGE 150*54fd6939SJiyong Park cmp x30, x0 151*54fd6939SJiyong Park b.ne smc_handler 152*54fd6939SJiyong Park 153*54fd6939SJiyong Park /* ------------------------------------------------ 154*54fd6939SJiyong Park * Make sure only Secure world reaches here. 155*54fd6939SJiyong Park * ------------------------------------------------ 156*54fd6939SJiyong Park */ 157*54fd6939SJiyong Park mrs x30, scr_el3 158*54fd6939SJiyong Park tst x30, #SCR_NS_BIT 159*54fd6939SJiyong Park b.ne unexpected_sync_exception 160*54fd6939SJiyong Park 161*54fd6939SJiyong Park /* ---------------------------------------------- 162*54fd6939SJiyong Park * Handling RUN_IMAGE SMC. First switch back to 163*54fd6939SJiyong Park * SP_EL0 for the C runtime stack. 164*54fd6939SJiyong Park * ---------------------------------------------- 165*54fd6939SJiyong Park */ 166*54fd6939SJiyong Park ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 167*54fd6939SJiyong Park msr spsel, #MODE_SP_EL0 168*54fd6939SJiyong Park mov sp, x30 169*54fd6939SJiyong Park 170*54fd6939SJiyong Park /* --------------------------------------------------------------------- 171*54fd6939SJiyong Park * Pass EL3 control to next BL image. 172*54fd6939SJiyong Park * Here it expects X1 with the address of a entry_point_info_t 173*54fd6939SJiyong Park * structure describing the next BL image entrypoint. 174*54fd6939SJiyong Park * --------------------------------------------------------------------- 175*54fd6939SJiyong Park */ 176*54fd6939SJiyong Park mov x20, x1 177*54fd6939SJiyong Park 178*54fd6939SJiyong Park mov x0, x20 179*54fd6939SJiyong Park bl bl1_print_next_bl_ep_info 180*54fd6939SJiyong Park 181*54fd6939SJiyong Park ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 182*54fd6939SJiyong Park msr elr_el3, x0 183*54fd6939SJiyong Park msr spsr_el3, x1 184*54fd6939SJiyong Park ubfx x0, x1, #MODE_EL_SHIFT, #2 185*54fd6939SJiyong Park cmp x0, #MODE_EL3 186*54fd6939SJiyong Park b.ne unexpected_sync_exception 187*54fd6939SJiyong Park 188*54fd6939SJiyong Park bl disable_mmu_icache_el3 189*54fd6939SJiyong Park tlbi alle3 190*54fd6939SJiyong Park dsb ish /* ERET implies ISB, so it is not needed here */ 191*54fd6939SJiyong Park 192*54fd6939SJiyong Park#if SPIN_ON_BL1_EXIT 193*54fd6939SJiyong Park bl print_debug_loop_message 194*54fd6939SJiyong Parkdebug_loop: 195*54fd6939SJiyong Park b debug_loop 196*54fd6939SJiyong Park#endif 197*54fd6939SJiyong Park 198*54fd6939SJiyong Park mov x0, x20 199*54fd6939SJiyong Park bl bl1_plat_prepare_exit 200*54fd6939SJiyong Park 201*54fd6939SJiyong Park ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 202*54fd6939SJiyong Park ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 203*54fd6939SJiyong Park ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 204*54fd6939SJiyong Park ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 205*54fd6939SJiyong Park exception_return 206*54fd6939SJiyong Parkendfunc smc_handler64 207*54fd6939SJiyong Park 208*54fd6939SJiyong Parkunexpected_sync_exception: 209*54fd6939SJiyong Park mov x0, #SYNC_EXCEPTION_AARCH64 210*54fd6939SJiyong Park bl plat_report_exception 211*54fd6939SJiyong Park no_ret plat_panic_handler 212*54fd6939SJiyong Park 213*54fd6939SJiyong Park /* ----------------------------------------------------- 214*54fd6939SJiyong Park * Save Secure/Normal world context and jump to 215*54fd6939SJiyong Park * BL1 SMC handler. 216*54fd6939SJiyong Park * ----------------------------------------------------- 217*54fd6939SJiyong Park */ 218*54fd6939SJiyong Parksmc_handler: 219*54fd6939SJiyong Park /* ----------------------------------------------------- 220*54fd6939SJiyong Park * Save x0-x29 and ARMv8.3-PAuth (if enabled) registers. 221*54fd6939SJiyong Park * If Secure Cycle Counter is not disabled in MDCR_EL3 222*54fd6939SJiyong Park * when ARMv8.5-PMU is implemented, save PMCR_EL0 and 223*54fd6939SJiyong Park * disable Cycle Counter. 224*54fd6939SJiyong Park * TODO: Revisit to store only SMCCC specified registers. 225*54fd6939SJiyong Park * ----------------------------------------------------- 226*54fd6939SJiyong Park */ 227*54fd6939SJiyong Park bl save_gp_pmcr_pauth_regs 228*54fd6939SJiyong Park 229*54fd6939SJiyong Park#if ENABLE_PAUTH 230*54fd6939SJiyong Park /* ----------------------------------------------------- 231*54fd6939SJiyong Park * Load and program stored APIAKey firmware key. 232*54fd6939SJiyong Park * Re-enable pointer authentication in EL3, as it was 233*54fd6939SJiyong Park * disabled before jumping to the next boot image. 234*54fd6939SJiyong Park * ----------------------------------------------------- 235*54fd6939SJiyong Park */ 236*54fd6939SJiyong Park bl pauth_load_bl1_apiakey_enable 237*54fd6939SJiyong Park#endif 238*54fd6939SJiyong Park /* ----------------------------------------------------- 239*54fd6939SJiyong Park * Populate the parameters for the SMC handler. We 240*54fd6939SJiyong Park * already have x0-x4 in place. x5 will point to a 241*54fd6939SJiyong Park * cookie (not used now). x6 will point to the context 242*54fd6939SJiyong Park * structure (SP_EL3) and x7 will contain flags we need 243*54fd6939SJiyong Park * to pass to the handler. 244*54fd6939SJiyong Park * ----------------------------------------------------- 245*54fd6939SJiyong Park */ 246*54fd6939SJiyong Park mov x5, xzr 247*54fd6939SJiyong Park mov x6, sp 248*54fd6939SJiyong Park 249*54fd6939SJiyong Park /* ----------------------------------------------------- 250*54fd6939SJiyong Park * Restore the saved C runtime stack value which will 251*54fd6939SJiyong Park * become the new SP_EL0 i.e. EL3 runtime stack. It was 252*54fd6939SJiyong Park * saved in the 'cpu_context' structure prior to the last 253*54fd6939SJiyong Park * ERET from EL3. 254*54fd6939SJiyong Park * ----------------------------------------------------- 255*54fd6939SJiyong Park */ 256*54fd6939SJiyong Park ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 257*54fd6939SJiyong Park 258*54fd6939SJiyong Park /* --------------------------------------------- 259*54fd6939SJiyong Park * Switch back to SP_EL0 for the C runtime stack. 260*54fd6939SJiyong Park * --------------------------------------------- 261*54fd6939SJiyong Park */ 262*54fd6939SJiyong Park msr spsel, #MODE_SP_EL0 263*54fd6939SJiyong Park mov sp, x12 264*54fd6939SJiyong Park 265*54fd6939SJiyong Park /* ----------------------------------------------------- 266*54fd6939SJiyong Park * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there 267*54fd6939SJiyong Park * is a world switch during SMC handling. 268*54fd6939SJiyong Park * ----------------------------------------------------- 269*54fd6939SJiyong Park */ 270*54fd6939SJiyong Park mrs x16, spsr_el3 271*54fd6939SJiyong Park mrs x17, elr_el3 272*54fd6939SJiyong Park mrs x18, scr_el3 273*54fd6939SJiyong Park stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 274*54fd6939SJiyong Park str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 275*54fd6939SJiyong Park 276*54fd6939SJiyong Park /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 277*54fd6939SJiyong Park bfi x7, x18, #0, #1 278*54fd6939SJiyong Park 279*54fd6939SJiyong Park /* ----------------------------------------------------- 280*54fd6939SJiyong Park * Go to BL1 SMC handler. 281*54fd6939SJiyong Park * ----------------------------------------------------- 282*54fd6939SJiyong Park */ 283*54fd6939SJiyong Park bl bl1_smc_handler 284*54fd6939SJiyong Park 285*54fd6939SJiyong Park /* ----------------------------------------------------- 286*54fd6939SJiyong Park * Do the transition to next BL image. 287*54fd6939SJiyong Park * ----------------------------------------------------- 288*54fd6939SJiyong Park */ 289*54fd6939SJiyong Park b el3_exit 290