1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <arch.h> 8*54fd6939SJiyong Park#include <asm_macros.S> 9*54fd6939SJiyong Park#include <common/bl_common.h> 10*54fd6939SJiyong Park#include <context.h> 11*54fd6939SJiyong Park#include <el3_common_macros.S> 12*54fd6939SJiyong Park#include <smccc_helpers.h> 13*54fd6939SJiyong Park#include <smccc_macros.S> 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park .globl bl1_vector_table 16*54fd6939SJiyong Park .globl bl1_entrypoint 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park /* ----------------------------------------------------- 19*54fd6939SJiyong Park * Setup the vector table to support SVC & MON mode. 20*54fd6939SJiyong Park * ----------------------------------------------------- 21*54fd6939SJiyong Park */ 22*54fd6939SJiyong Parkvector_base bl1_vector_table 23*54fd6939SJiyong Park b bl1_entrypoint 24*54fd6939SJiyong Park b report_exception /* Undef */ 25*54fd6939SJiyong Park b bl1_aarch32_smc_handler /* SMC call */ 26*54fd6939SJiyong Park b report_exception /* Prefetch abort */ 27*54fd6939SJiyong Park b report_exception /* Data abort */ 28*54fd6939SJiyong Park b report_exception /* Reserved */ 29*54fd6939SJiyong Park b report_exception /* IRQ */ 30*54fd6939SJiyong Park b report_exception /* FIQ */ 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park /* ----------------------------------------------------- 33*54fd6939SJiyong Park * bl1_entrypoint() is the entry point into the trusted 34*54fd6939SJiyong Park * firmware code when a cpu is released from warm or 35*54fd6939SJiyong Park * cold reset. 36*54fd6939SJiyong Park * ----------------------------------------------------- 37*54fd6939SJiyong Park */ 38*54fd6939SJiyong Park 39*54fd6939SJiyong Parkfunc bl1_entrypoint 40*54fd6939SJiyong Park/* --------------------------------------------------------------------- 41*54fd6939SJiyong Park* If the reset address is programmable then bl1_entrypoint() is 42*54fd6939SJiyong Park* executed only on the cold boot path. Therefore, we can skip the warm 43*54fd6939SJiyong Park* boot mailbox mechanism. 44*54fd6939SJiyong Park* --------------------------------------------------------------------- 45*54fd6939SJiyong Park*/ 46*54fd6939SJiyong Park el3_entrypoint_common \ 47*54fd6939SJiyong Park _init_sctlr=1 \ 48*54fd6939SJiyong Park _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 49*54fd6939SJiyong Park _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 50*54fd6939SJiyong Park _init_memory=1 \ 51*54fd6939SJiyong Park _init_c_runtime=1 \ 52*54fd6939SJiyong Park _exception_vectors=bl1_vector_table \ 53*54fd6939SJiyong Park _pie_fixup_size=0 54*54fd6939SJiyong Park 55*54fd6939SJiyong Park /* ----------------------------------------------------- 56*54fd6939SJiyong Park * Perform BL1 setup 57*54fd6939SJiyong Park * ----------------------------------------------------- 58*54fd6939SJiyong Park */ 59*54fd6939SJiyong Park bl bl1_setup 60*54fd6939SJiyong Park 61*54fd6939SJiyong Park /* ----------------------------------------------------- 62*54fd6939SJiyong Park * Jump to main function. 63*54fd6939SJiyong Park * ----------------------------------------------------- 64*54fd6939SJiyong Park */ 65*54fd6939SJiyong Park bl bl1_main 66*54fd6939SJiyong Park 67*54fd6939SJiyong Park /* ----------------------------------------------------- 68*54fd6939SJiyong Park * Jump to next image. 69*54fd6939SJiyong Park * ----------------------------------------------------- 70*54fd6939SJiyong Park */ 71*54fd6939SJiyong Park 72*54fd6939SJiyong Park /* 73*54fd6939SJiyong Park * Get the smc_context for next BL image, 74*54fd6939SJiyong Park * program the gp/system registers and save it in `r4`. 75*54fd6939SJiyong Park */ 76*54fd6939SJiyong Park bl smc_get_next_ctx 77*54fd6939SJiyong Park mov r4, r0 78*54fd6939SJiyong Park 79*54fd6939SJiyong Park /* Only turn-off MMU if going to secure world */ 80*54fd6939SJiyong Park ldr r5, [r4, #SMC_CTX_SCR] 81*54fd6939SJiyong Park tst r5, #SCR_NS_BIT 82*54fd6939SJiyong Park bne skip_mmu_off 83*54fd6939SJiyong Park 84*54fd6939SJiyong Park /* 85*54fd6939SJiyong Park * MMU needs to be disabled because both BL1 and BL2/BL2U execute 86*54fd6939SJiyong Park * in PL1, and therefore share the same address space. 87*54fd6939SJiyong Park * BL2/BL2U will initialize the address space according to its 88*54fd6939SJiyong Park * own requirement. 89*54fd6939SJiyong Park */ 90*54fd6939SJiyong Park bl disable_mmu_icache_secure 91*54fd6939SJiyong Park stcopr r0, TLBIALL 92*54fd6939SJiyong Park dsb sy 93*54fd6939SJiyong Park isb 94*54fd6939SJiyong Park 95*54fd6939SJiyong Parkskip_mmu_off: 96*54fd6939SJiyong Park /* Restore smc_context from `r4` and exit secure monitor mode. */ 97*54fd6939SJiyong Park mov r0, r4 98*54fd6939SJiyong Park monitor_exit 99*54fd6939SJiyong Parkendfunc bl1_entrypoint 100