1*412f47f9SXin Li/* 2*412f47f9SXin Li * strcmp for ARMv6-M (optimized for performance, not size) 3*412f47f9SXin Li * 4*412f47f9SXin Li * Copyright (c) 2014-2022, Arm Limited. 5*412f47f9SXin Li * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6*412f47f9SXin Li */ 7*412f47f9SXin Li 8*412f47f9SXin Li#include "asmdefs.h" 9*412f47f9SXin Li 10*412f47f9SXin Li#if __ARM_ARCH == 6 && __ARM_ARCH_6M__ >= 1 11*412f47f9SXin Li 12*412f47f9SXin Li .thumb_func 13*412f47f9SXin Li .syntax unified 14*412f47f9SXin Li .arch armv6-m 15*412f47f9SXin Li 16*412f47f9SXin Li .macro DoSub n, label 17*412f47f9SXin Li subs r0, r0, r1 18*412f47f9SXin Li#ifdef __ARM_BIG_ENDIAN 19*412f47f9SXin Li lsrs r1, r4, \n 20*412f47f9SXin Li#else 21*412f47f9SXin Li lsls r1, r4, \n 22*412f47f9SXin Li#endif 23*412f47f9SXin Li orrs r1, r0 24*412f47f9SXin Li bne \label 25*412f47f9SXin Li .endm 26*412f47f9SXin Li 27*412f47f9SXin Li .macro Byte_Test n, label 28*412f47f9SXin Li lsrs r0, r2, \n 29*412f47f9SXin Li lsrs r1, r3, \n 30*412f47f9SXin Li DoSub \n, \label 31*412f47f9SXin Li .endm 32*412f47f9SXin Li 33*412f47f9SXin LiENTRY_ALIGN (__strcmp_armv6m, 4) 34*412f47f9SXin Li mov r2, r0 35*412f47f9SXin Li push {r4, r5, r6, lr} 36*412f47f9SXin Li orrs r2, r1 37*412f47f9SXin Li lsls r2, r2, #30 38*412f47f9SXin Li bne 6f 39*412f47f9SXin Li ldr r5, =0x01010101 40*412f47f9SXin Li lsls r6, r5, #7 41*412f47f9SXin Li1: 42*412f47f9SXin Li ldmia r0!, {r2} 43*412f47f9SXin Li ldmia r1!, {r3} 44*412f47f9SXin Li subs r4, r2, r5 45*412f47f9SXin Li bics r4, r2 46*412f47f9SXin Li ands r4, r6 47*412f47f9SXin Li beq 3f 48*412f47f9SXin Li 49*412f47f9SXin Li#ifdef __ARM_BIG_ENDIAN 50*412f47f9SXin Li Byte_Test #24, 4f 51*412f47f9SXin Li Byte_Test #16, 4f 52*412f47f9SXin Li Byte_Test #8, 4f 53*412f47f9SXin Li 54*412f47f9SXin Li b 7f 55*412f47f9SXin Li3: 56*412f47f9SXin Li cmp r2, r3 57*412f47f9SXin Li beq 1b 58*412f47f9SXin Li cmp r2, r3 59*412f47f9SXin Li#else 60*412f47f9SXin Li uxtb r0, r2 61*412f47f9SXin Li uxtb r1, r3 62*412f47f9SXin Li DoSub #24, 2f 63*412f47f9SXin Li 64*412f47f9SXin Li uxth r0, r2 65*412f47f9SXin Li uxth r1, r3 66*412f47f9SXin Li DoSub #16, 2f 67*412f47f9SXin Li 68*412f47f9SXin Li lsls r0, r2, #8 69*412f47f9SXin Li lsls r1, r3, #8 70*412f47f9SXin Li lsrs r0, r0, #8 71*412f47f9SXin Li lsrs r1, r1, #8 72*412f47f9SXin Li DoSub #8, 2f 73*412f47f9SXin Li 74*412f47f9SXin Li lsrs r0, r2, #24 75*412f47f9SXin Li lsrs r1, r3, #24 76*412f47f9SXin Li subs r0, r0, r1 77*412f47f9SXin Li2: 78*412f47f9SXin Li pop {r4, r5, r6, pc} 79*412f47f9SXin Li 80*412f47f9SXin Li3: 81*412f47f9SXin Li cmp r2, r3 82*412f47f9SXin Li beq 1b 83*412f47f9SXin Li rev r0, r2 84*412f47f9SXin Li rev r1, r3 85*412f47f9SXin Li cmp r0, r1 86*412f47f9SXin Li#endif 87*412f47f9SXin Li 88*412f47f9SXin Li bls 5f 89*412f47f9SXin Li movs r0, #1 90*412f47f9SXin Li4: 91*412f47f9SXin Li pop {r4, r5, r6, pc} 92*412f47f9SXin Li5: 93*412f47f9SXin Li movs r0, #0 94*412f47f9SXin Li mvns r0, r0 95*412f47f9SXin Li pop {r4, r5, r6, pc} 96*412f47f9SXin Li6: 97*412f47f9SXin Li ldrb r2, [r0, #0] 98*412f47f9SXin Li ldrb r3, [r1, #0] 99*412f47f9SXin Li adds r0, #1 100*412f47f9SXin Li adds r1, #1 101*412f47f9SXin Li cmp r2, #0 102*412f47f9SXin Li beq 7f 103*412f47f9SXin Li cmp r2, r3 104*412f47f9SXin Li bne 7f 105*412f47f9SXin Li ldrb r2, [r0, #0] 106*412f47f9SXin Li ldrb r3, [r1, #0] 107*412f47f9SXin Li adds r0, #1 108*412f47f9SXin Li adds r1, #1 109*412f47f9SXin Li cmp r2, #0 110*412f47f9SXin Li beq 7f 111*412f47f9SXin Li cmp r2, r3 112*412f47f9SXin Li beq 6b 113*412f47f9SXin Li7: 114*412f47f9SXin Li subs r0, r2, r3 115*412f47f9SXin Li pop {r4, r5, r6, pc} 116*412f47f9SXin Li 117*412f47f9SXin LiEND (__strcmp_armv6m) 118*412f47f9SXin Li 119*412f47f9SXin Li#endif /* __ARM_ARCH == 6 && __ARM_ARCH_6M__ >= 1 */ 120