xref: /aosp_15_r20/external/arm-optimized-routines/pl/math/v_sinpi_3u1.c (revision 412f47f9e737e10ed5cc46ec6a8d7fa2264f8a14)
1*412f47f9SXin Li /*
2*412f47f9SXin Li  * Double-precision vector sinpi function.
3*412f47f9SXin Li  *
4*412f47f9SXin Li  * Copyright (c) 2023, Arm Limited.
5*412f47f9SXin Li  * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6*412f47f9SXin Li  */
7*412f47f9SXin Li 
8*412f47f9SXin Li #include "mathlib.h"
9*412f47f9SXin Li #include "v_math.h"
10*412f47f9SXin Li #include "poly_advsimd_f64.h"
11*412f47f9SXin Li #include "pl_sig.h"
12*412f47f9SXin Li #include "pl_test.h"
13*412f47f9SXin Li 
14*412f47f9SXin Li static const struct data
15*412f47f9SXin Li {
16*412f47f9SXin Li   float64x2_t poly[10];
17*412f47f9SXin Li } data = {
18*412f47f9SXin Li   /* Polynomial coefficients generated using Remez algorithm,
19*412f47f9SXin Li      see sinpi.sollya for details.  */
20*412f47f9SXin Li   .poly = { V2 (0x1.921fb54442d184p1), V2 (-0x1.4abbce625be53p2),
21*412f47f9SXin Li 	    V2 (0x1.466bc6775ab16p1), V2 (-0x1.32d2cce62dc33p-1),
22*412f47f9SXin Li 	    V2 (0x1.507834891188ep-4), V2 (-0x1.e30750a28c88ep-8),
23*412f47f9SXin Li 	    V2 (0x1.e8f48308acda4p-12), V2 (-0x1.6fc0032b3c29fp-16),
24*412f47f9SXin Li 	    V2 (0x1.af86ae521260bp-21), V2 (-0x1.012a9870eeb7dp-25) },
25*412f47f9SXin Li };
26*412f47f9SXin Li 
27*412f47f9SXin Li #if WANT_SIMD_EXCEPT
28*412f47f9SXin Li # define TinyBound v_u64 (0x3bf0000000000000) /* asuint64(0x1p-64).  */
29*412f47f9SXin Li /* asuint64(0x1p64) - TinyBound.  */
30*412f47f9SXin Li # define Thresh v_u64 (0x07f0000000000000)
31*412f47f9SXin Li 
32*412f47f9SXin Li static float64x2_t VPCS_ATTR NOINLINE
special_case(float64x2_t x,float64x2_t y,uint64x2_t odd,uint64x2_t cmp)33*412f47f9SXin Li special_case (float64x2_t x, float64x2_t y, uint64x2_t odd, uint64x2_t cmp)
34*412f47f9SXin Li {
35*412f47f9SXin Li   /* Fall back to scalar code.  */
36*412f47f9SXin Li   y = vreinterpretq_f64_u64 (veorq_u64 (vreinterpretq_u64_f64 (y), odd));
37*412f47f9SXin Li   return v_call_f64 (sinpi, x, y, cmp);
38*412f47f9SXin Li }
39*412f47f9SXin Li #endif
40*412f47f9SXin Li 
41*412f47f9SXin Li /* Approximation for vector double-precision sinpi(x).
42*412f47f9SXin Li    Maximum Error 3.05 ULP:
43*412f47f9SXin Li   _ZGVnN2v_sinpi(0x1.d32750db30b4ap-2) got 0x1.fb295878301c7p-1
44*412f47f9SXin Li 				      want 0x1.fb295878301cap-1.  */
V_NAME_D1(sinpi)45*412f47f9SXin Li float64x2_t VPCS_ATTR V_NAME_D1 (sinpi) (float64x2_t x)
46*412f47f9SXin Li {
47*412f47f9SXin Li   const struct data *d = ptr_barrier (&data);
48*412f47f9SXin Li 
49*412f47f9SXin Li #if WANT_SIMD_EXCEPT
50*412f47f9SXin Li   uint64x2_t ir = vreinterpretq_u64_f64 (vabsq_f64 (x));
51*412f47f9SXin Li   uint64x2_t cmp = vcgeq_u64 (vsubq_u64 (ir, TinyBound), Thresh);
52*412f47f9SXin Li 
53*412f47f9SXin Li   /* When WANT_SIMD_EXCEPT = 1, special lanes should be set to 0
54*412f47f9SXin Li      to avoid them under/overflowing and throwing exceptions.  */
55*412f47f9SXin Li   float64x2_t r = v_zerofy_f64 (x, cmp);
56*412f47f9SXin Li #else
57*412f47f9SXin Li   float64x2_t r = x;
58*412f47f9SXin Li #endif
59*412f47f9SXin Li 
60*412f47f9SXin Li   /* If r is odd, the sign of the result should be inverted.  */
61*412f47f9SXin Li   uint64x2_t odd
62*412f47f9SXin Li       = vshlq_n_u64 (vreinterpretq_u64_s64 (vcvtaq_s64_f64 (r)), 63);
63*412f47f9SXin Li 
64*412f47f9SXin Li   /* r = x - rint(x). Range reduction to -1/2 .. 1/2.  */
65*412f47f9SXin Li   r = vsubq_f64 (r, vrndaq_f64 (r));
66*412f47f9SXin Li 
67*412f47f9SXin Li   /* y = sin(r).  */
68*412f47f9SXin Li   float64x2_t r2 = vmulq_f64 (r, r);
69*412f47f9SXin Li   float64x2_t r4 = vmulq_f64 (r2, r2);
70*412f47f9SXin Li   float64x2_t y = vmulq_f64 (v_pw_horner_9_f64 (r2, r4, d->poly), r);
71*412f47f9SXin Li 
72*412f47f9SXin Li #if WANT_SIMD_EXCEPT
73*412f47f9SXin Li   if (unlikely (v_any_u64 (cmp)))
74*412f47f9SXin Li     return special_case (x, y, odd, cmp);
75*412f47f9SXin Li #endif
76*412f47f9SXin Li 
77*412f47f9SXin Li   return vreinterpretq_f64_u64 (veorq_u64 (vreinterpretq_u64_f64 (y), odd));
78*412f47f9SXin Li }
79*412f47f9SXin Li 
80*412f47f9SXin Li PL_SIG (V, D, 1, sinpi, -0.9, 0.9)
81*412f47f9SXin Li PL_TEST_ULP (V_NAME_D1 (sinpi), 3.06)
82*412f47f9SXin Li PL_TEST_EXPECT_FENV (V_NAME_D1 (sinpi), WANT_SIMD_EXCEPT)
83*412f47f9SXin Li PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinpi), 0, 0x1p-63, 5000)
84*412f47f9SXin Li PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinpi), 0x1p-63, 0.5, 10000)
85*412f47f9SXin Li PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinpi), 0.5, 0x1p51, 10000)
86*412f47f9SXin Li PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinpi), 0x1p51, inf, 10000)
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