1*412f47f9SXin Li /*
2*412f47f9SXin Li * Single-precision vector log2 function.
3*412f47f9SXin Li *
4*412f47f9SXin Li * Copyright (c) 2022-2023, Arm Limited.
5*412f47f9SXin Li * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6*412f47f9SXin Li */
7*412f47f9SXin Li
8*412f47f9SXin Li #include "v_math.h"
9*412f47f9SXin Li #include "poly_advsimd_f32.h"
10*412f47f9SXin Li #include "pl_sig.h"
11*412f47f9SXin Li #include "pl_test.h"
12*412f47f9SXin Li
13*412f47f9SXin Li static const struct data
14*412f47f9SXin Li {
15*412f47f9SXin Li uint32x4_t min_norm;
16*412f47f9SXin Li uint16x8_t special_bound;
17*412f47f9SXin Li uint32x4_t off, mantissa_mask;
18*412f47f9SXin Li float32x4_t poly[9];
19*412f47f9SXin Li } data = {
20*412f47f9SXin Li /* Coefficients generated using Remez algorithm approximate
21*412f47f9SXin Li log2(1+r)/r for r in [ -1/3, 1/3 ].
22*412f47f9SXin Li rel error: 0x1.c4c4b0cp-26. */
23*412f47f9SXin Li .poly = { V4 (0x1.715476p0f), /* (float)(1 / ln(2)). */
24*412f47f9SXin Li V4 (-0x1.715458p-1f), V4 (0x1.ec701cp-2f), V4 (-0x1.7171a4p-2f),
25*412f47f9SXin Li V4 (0x1.27a0b8p-2f), V4 (-0x1.e5143ep-3f), V4 (0x1.9d8ecap-3f),
26*412f47f9SXin Li V4 (-0x1.c675bp-3f), V4 (0x1.9e495p-3f) },
27*412f47f9SXin Li .min_norm = V4 (0x00800000),
28*412f47f9SXin Li .special_bound = V8 (0x7f00), /* asuint32(inf) - min_norm. */
29*412f47f9SXin Li .off = V4 (0x3f2aaaab), /* 0.666667. */
30*412f47f9SXin Li .mantissa_mask = V4 (0x007fffff),
31*412f47f9SXin Li };
32*412f47f9SXin Li
33*412f47f9SXin Li static float32x4_t VPCS_ATTR NOINLINE
special_case(float32x4_t x,float32x4_t n,float32x4_t p,float32x4_t r,uint16x4_t cmp)34*412f47f9SXin Li special_case (float32x4_t x, float32x4_t n, float32x4_t p, float32x4_t r,
35*412f47f9SXin Li uint16x4_t cmp)
36*412f47f9SXin Li {
37*412f47f9SXin Li /* Fall back to scalar code. */
38*412f47f9SXin Li return v_call_f32 (log2f, x, vfmaq_f32 (n, p, r), vmovl_u16 (cmp));
39*412f47f9SXin Li }
40*412f47f9SXin Li
41*412f47f9SXin Li /* Fast implementation for single precision AdvSIMD log2,
42*412f47f9SXin Li relies on same argument reduction as AdvSIMD logf.
43*412f47f9SXin Li Maximum error: 2.48 ULPs
44*412f47f9SXin Li _ZGVnN4v_log2f(0x1.558174p+0) got 0x1.a9be84p-2
45*412f47f9SXin Li want 0x1.a9be8p-2. */
V_NAME_F1(log2)46*412f47f9SXin Li float32x4_t VPCS_ATTR V_NAME_F1 (log2) (float32x4_t x)
47*412f47f9SXin Li {
48*412f47f9SXin Li const struct data *d = ptr_barrier (&data);
49*412f47f9SXin Li uint32x4_t u = vreinterpretq_u32_f32 (x);
50*412f47f9SXin Li uint16x4_t special = vcge_u16 (vsubhn_u32 (u, d->min_norm),
51*412f47f9SXin Li vget_low_u16 (d->special_bound));
52*412f47f9SXin Li
53*412f47f9SXin Li /* x = 2^n * (1+r), where 2/3 < 1+r < 4/3. */
54*412f47f9SXin Li u = vsubq_u32 (u, d->off);
55*412f47f9SXin Li float32x4_t n = vcvtq_f32_s32 (
56*412f47f9SXin Li vshrq_n_s32 (vreinterpretq_s32_u32 (u), 23)); /* signextend. */
57*412f47f9SXin Li u = vaddq_u32 (vandq_u32 (u, d->mantissa_mask), d->off);
58*412f47f9SXin Li float32x4_t r = vsubq_f32 (vreinterpretq_f32_u32 (u), v_f32 (1.0f));
59*412f47f9SXin Li
60*412f47f9SXin Li /* y = log2(1+r) + n. */
61*412f47f9SXin Li float32x4_t r2 = vmulq_f32 (r, r);
62*412f47f9SXin Li float32x4_t p = v_pw_horner_8_f32 (r, r2, d->poly);
63*412f47f9SXin Li
64*412f47f9SXin Li if (unlikely (v_any_u16h (special)))
65*412f47f9SXin Li return special_case (x, n, p, r, special);
66*412f47f9SXin Li return vfmaq_f32 (n, p, r);
67*412f47f9SXin Li }
68*412f47f9SXin Li
69*412f47f9SXin Li PL_SIG (V, F, 1, log2, 0.01, 11.1)
70*412f47f9SXin Li PL_TEST_ULP (V_NAME_F1 (log2), 1.99)
71*412f47f9SXin Li PL_TEST_EXPECT_FENV_ALWAYS (V_NAME_F1 (log2))
72*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log2), -0.0, -0x1p126, 100)
73*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log2), 0x1p-149, 0x1p-126, 4000)
74*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log2), 0x1p-126, 0x1p-23, 50000)
75*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log2), 0x1p-23, 1.0, 50000)
76*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log2), 1.0, 100, 50000)
77*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log2), 100, inf, 50000)
78