xref: /aosp_15_r20/external/arm-optimized-routines/pl/math/v_log10f_3u5.c (revision 412f47f9e737e10ed5cc46ec6a8d7fa2264f8a14)
1*412f47f9SXin Li /*
2*412f47f9SXin Li  * Single-precision vector log10 function.
3*412f47f9SXin Li  *
4*412f47f9SXin Li  * Copyright (c) 2020-2023, Arm Limited.
5*412f47f9SXin Li  * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6*412f47f9SXin Li  */
7*412f47f9SXin Li 
8*412f47f9SXin Li #include "v_math.h"
9*412f47f9SXin Li #include "poly_advsimd_f32.h"
10*412f47f9SXin Li #include "pl_sig.h"
11*412f47f9SXin Li #include "pl_test.h"
12*412f47f9SXin Li 
13*412f47f9SXin Li static const struct data
14*412f47f9SXin Li {
15*412f47f9SXin Li   uint32x4_t min_norm;
16*412f47f9SXin Li   uint16x8_t special_bound;
17*412f47f9SXin Li   float32x4_t poly[8];
18*412f47f9SXin Li   float32x4_t inv_ln10, ln2;
19*412f47f9SXin Li   uint32x4_t off, mantissa_mask;
20*412f47f9SXin Li } data = {
21*412f47f9SXin Li   /* Use order 9 for log10(1+x), i.e. order 8 for log10(1+x)/x, with x in
22*412f47f9SXin Li       [-1/3, 1/3] (offset=2/3). Max. relative error: 0x1.068ee468p-25.  */
23*412f47f9SXin Li   .poly = { V4 (-0x1.bcb79cp-3f), V4 (0x1.2879c8p-3f), V4 (-0x1.bcd472p-4f),
24*412f47f9SXin Li 	    V4 (0x1.6408f8p-4f), V4 (-0x1.246f8p-4f), V4 (0x1.f0e514p-5f),
25*412f47f9SXin Li 	    V4 (-0x1.0fc92cp-4f), V4 (0x1.f5f76ap-5f) },
26*412f47f9SXin Li   .ln2 = V4 (0x1.62e43p-1f),
27*412f47f9SXin Li   .inv_ln10 = V4 (0x1.bcb7b2p-2f),
28*412f47f9SXin Li   .min_norm = V4 (0x00800000),
29*412f47f9SXin Li   .special_bound = V8 (0x7f00), /* asuint32(inf) - min_norm.  */
30*412f47f9SXin Li   .off = V4 (0x3f2aaaab),	/* 0.666667.  */
31*412f47f9SXin Li   .mantissa_mask = V4 (0x007fffff),
32*412f47f9SXin Li };
33*412f47f9SXin Li 
34*412f47f9SXin Li static float32x4_t VPCS_ATTR NOINLINE
special_case(float32x4_t x,float32x4_t y,float32x4_t p,float32x4_t r2,uint16x4_t cmp)35*412f47f9SXin Li special_case (float32x4_t x, float32x4_t y, float32x4_t p, float32x4_t r2,
36*412f47f9SXin Li 	      uint16x4_t cmp)
37*412f47f9SXin Li {
38*412f47f9SXin Li   /* Fall back to scalar code.  */
39*412f47f9SXin Li   return v_call_f32 (log10f, x, vfmaq_f32 (y, p, r2), vmovl_u16 (cmp));
40*412f47f9SXin Li }
41*412f47f9SXin Li 
42*412f47f9SXin Li /* Fast implementation of AdvSIMD log10f,
43*412f47f9SXin Li    uses a similar approach as AdvSIMD logf with the same offset (i.e., 2/3) and
44*412f47f9SXin Li    an order 9 polynomial.
45*412f47f9SXin Li    Maximum error: 3.305ulps (nearest rounding.)
46*412f47f9SXin Li    _ZGVnN4v_log10f(0x1.555c16p+0) got 0x1.ffe2fap-4
47*412f47f9SXin Li 				 want 0x1.ffe2f4p-4.  */
V_NAME_F1(log10)48*412f47f9SXin Li float32x4_t VPCS_ATTR V_NAME_F1 (log10) (float32x4_t x)
49*412f47f9SXin Li {
50*412f47f9SXin Li   const struct data *d = ptr_barrier (&data);
51*412f47f9SXin Li   uint32x4_t u = vreinterpretq_u32_f32 (x);
52*412f47f9SXin Li   uint16x4_t special = vcge_u16 (vsubhn_u32 (u, d->min_norm),
53*412f47f9SXin Li 				 vget_low_u16 (d->special_bound));
54*412f47f9SXin Li 
55*412f47f9SXin Li   /* x = 2^n * (1+r), where 2/3 < 1+r < 4/3.  */
56*412f47f9SXin Li   u = vsubq_u32 (u, d->off);
57*412f47f9SXin Li   float32x4_t n = vcvtq_f32_s32 (
58*412f47f9SXin Li       vshrq_n_s32 (vreinterpretq_s32_u32 (u), 23)); /* signextend.  */
59*412f47f9SXin Li   u = vaddq_u32 (vandq_u32 (u, d->mantissa_mask), d->off);
60*412f47f9SXin Li   float32x4_t r = vsubq_f32 (vreinterpretq_f32_u32 (u), v_f32 (1.0f));
61*412f47f9SXin Li 
62*412f47f9SXin Li   /* y = log10(1+r) + n * log10(2).  */
63*412f47f9SXin Li   float32x4_t r2 = vmulq_f32 (r, r);
64*412f47f9SXin Li   float32x4_t poly = v_pw_horner_7_f32 (r, r2, d->poly);
65*412f47f9SXin Li   /* y = Log10(2) * n + poly * InvLn(10).  */
66*412f47f9SXin Li   float32x4_t y = vfmaq_f32 (r, d->ln2, n);
67*412f47f9SXin Li   y = vmulq_f32 (y, d->inv_ln10);
68*412f47f9SXin Li 
69*412f47f9SXin Li   if (unlikely (v_any_u16h (special)))
70*412f47f9SXin Li     return special_case (x, y, poly, r2, special);
71*412f47f9SXin Li   return vfmaq_f32 (y, poly, r2);
72*412f47f9SXin Li }
73*412f47f9SXin Li 
74*412f47f9SXin Li PL_SIG (V, F, 1, log10, 0.01, 11.1)
75*412f47f9SXin Li PL_TEST_ULP (V_NAME_F1 (log10), 2.81)
76*412f47f9SXin Li PL_TEST_EXPECT_FENV_ALWAYS (V_NAME_F1 (log10))
77*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log10), -0.0, -inf, 100)
78*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log10), 0, 0x1p-126, 100)
79*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log10), 0x1p-126, 0x1p-23, 50000)
80*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log10), 0x1p-23, 1.0, 50000)
81*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log10), 1.0, 100, 50000)
82*412f47f9SXin Li PL_TEST_INTERVAL (V_NAME_F1 (log10), 100, inf, 50000)
83