1*412f47f9SXin Li /*
2*412f47f9SXin Li * Double-precision vector atanh(x) function.
3*412f47f9SXin Li *
4*412f47f9SXin Li * Copyright (c) 2022-2023, Arm Limited.
5*412f47f9SXin Li * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6*412f47f9SXin Li */
7*412f47f9SXin Li
8*412f47f9SXin Li #include "v_math.h"
9*412f47f9SXin Li #include "pl_sig.h"
10*412f47f9SXin Li #include "pl_test.h"
11*412f47f9SXin Li
12*412f47f9SXin Li #define WANT_V_LOG1P_K0_SHORTCUT 0
13*412f47f9SXin Li #include "v_log1p_inline.h"
14*412f47f9SXin Li
15*412f47f9SXin Li const static struct data
16*412f47f9SXin Li {
17*412f47f9SXin Li struct v_log1p_data log1p_consts;
18*412f47f9SXin Li uint64x2_t one, half;
19*412f47f9SXin Li } data = { .log1p_consts = V_LOG1P_CONSTANTS_TABLE,
20*412f47f9SXin Li .one = V2 (0x3ff0000000000000),
21*412f47f9SXin Li .half = V2 (0x3fe0000000000000) };
22*412f47f9SXin Li
23*412f47f9SXin Li static float64x2_t VPCS_ATTR NOINLINE
special_case(float64x2_t x,float64x2_t y,uint64x2_t special)24*412f47f9SXin Li special_case (float64x2_t x, float64x2_t y, uint64x2_t special)
25*412f47f9SXin Li {
26*412f47f9SXin Li return v_call_f64 (atanh, x, y, special);
27*412f47f9SXin Li }
28*412f47f9SXin Li
29*412f47f9SXin Li /* Approximation for vector double-precision atanh(x) using modified log1p.
30*412f47f9SXin Li The greatest observed error is 3.31 ULP:
31*412f47f9SXin Li _ZGVnN2v_atanh(0x1.ffae6288b601p-6) got 0x1.ffd8ff31b5019p-6
32*412f47f9SXin Li want 0x1.ffd8ff31b501cp-6. */
33*412f47f9SXin Li VPCS_ATTR
V_NAME_D1(atanh)34*412f47f9SXin Li float64x2_t V_NAME_D1 (atanh) (float64x2_t x)
35*412f47f9SXin Li {
36*412f47f9SXin Li const struct data *d = ptr_barrier (&data);
37*412f47f9SXin Li
38*412f47f9SXin Li float64x2_t ax = vabsq_f64 (x);
39*412f47f9SXin Li uint64x2_t ia = vreinterpretq_u64_f64 (ax);
40*412f47f9SXin Li uint64x2_t sign = veorq_u64 (vreinterpretq_u64_f64 (x), ia);
41*412f47f9SXin Li uint64x2_t special = vcgeq_u64 (ia, d->one);
42*412f47f9SXin Li float64x2_t halfsign = vreinterpretq_f64_u64 (vorrq_u64 (sign, d->half));
43*412f47f9SXin Li
44*412f47f9SXin Li #if WANT_SIMD_EXCEPT
45*412f47f9SXin Li ax = v_zerofy_f64 (ax, special);
46*412f47f9SXin Li #endif
47*412f47f9SXin Li
48*412f47f9SXin Li float64x2_t y;
49*412f47f9SXin Li y = vaddq_f64 (ax, ax);
50*412f47f9SXin Li y = vdivq_f64 (y, vsubq_f64 (v_f64 (1), ax));
51*412f47f9SXin Li y = log1p_inline (y, &d->log1p_consts);
52*412f47f9SXin Li
53*412f47f9SXin Li if (unlikely (v_any_u64 (special)))
54*412f47f9SXin Li return special_case (x, vmulq_f64 (y, halfsign), special);
55*412f47f9SXin Li return vmulq_f64 (y, halfsign);
56*412f47f9SXin Li }
57*412f47f9SXin Li
58*412f47f9SXin Li PL_SIG (V, D, 1, atanh, -1.0, 1.0)
59*412f47f9SXin Li PL_TEST_EXPECT_FENV (V_NAME_D1 (atanh), WANT_SIMD_EXCEPT)
60*412f47f9SXin Li PL_TEST_ULP (V_NAME_D1 (atanh), 3.32)
61*412f47f9SXin Li /* atanh is asymptotic at 1, which is the default control value - have to set
62*412f47f9SXin Li -c 0 specially to ensure fp exceptions are triggered correctly (choice of
63*412f47f9SXin Li control lane is irrelevant if fp exceptions are disabled). */
64*412f47f9SXin Li PL_TEST_SYM_INTERVAL_C (V_NAME_D1 (atanh), 0, 0x1p-23, 10000, 0)
65*412f47f9SXin Li PL_TEST_SYM_INTERVAL_C (V_NAME_D1 (atanh), 0x1p-23, 1, 90000, 0)
66*412f47f9SXin Li PL_TEST_SYM_INTERVAL_C (V_NAME_D1 (atanh), 1, inf, 100, 0)
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