1*f3782652STreehugger Robot; Copyright ARM Ltd 2005. All rights reserved. 2*f3782652STreehugger Robot 3*f3782652STreehugger Robot;================================================================== 4*f3782652STreehugger Robot; This code provides basic global enable for a Cortex-A8 cache 5*f3782652STreehugger Robot; and program flow prediction 6*f3782652STreehugger Robot; This code must be run from a privileged mode 7*f3782652STreehugger Robot;================================================================== 8*f3782652STreehugger Robot 9*f3782652STreehugger Robot AREA CORTEXA8CACHE, CODE, READONLY 10*f3782652STreehugger Robot EXPORT core_init 11*f3782652STreehugger Robot 12*f3782652STreehugger Robotcore_init 13*f3782652STreehugger Robot 14*f3782652STreehugger Robot;================================================================== 15*f3782652STreehugger Robot; Global Enable for Cortex-A8 Instruction and Data Caching 16*f3782652STreehugger Robot;================================================================== 17*f3782652STreehugger Robot 18*f3782652STreehugger Robot MRC p15, 0, r0, c1, c0, 0 ; read CP15 register 1 into r0 19*f3782652STreehugger Robot ORR r0, r0, #(0x1 <<12) ; enable I Cache 20*f3782652STreehugger Robot ;BIC r0, r0, #(0x1 <<12) ; Clear bit 0 21*f3782652STreehugger Robot ORR r0, r0, #(0x1 <<2) ; enable D Cache 22*f3782652STreehugger Robot ;BIC r0, r0, #(0x1 << 2) ; Clear bit 0 23*f3782652STreehugger Robot ORR r0, r0, #0x1 ; enable MMU 24*f3782652STreehugger Robot MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1 25*f3782652STreehugger Robot 26*f3782652STreehugger Robot;================================================================== 27*f3782652STreehugger Robot; Enable Cortex-A8 Level2 Unified Cache 28*f3782652STreehugger Robot;================================================================== 29*f3782652STreehugger Robot 30*f3782652STreehugger Robot MRC p15, 0, r0, c1, c0, 1 ; Read Auxiliary Control Register 31*f3782652STreehugger Robot ORR r0, r0, #2 ; L2EN bit, enable L2 cache 32*f3782652STreehugger Robot ;BIC r0, r0, #(0x1 << 1) ; L2EN bit, disable L2 cache 33*f3782652STreehugger Robot ;ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI 34*f3782652STreehugger Robot ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI 35*f3782652STreehugger Robot ORR r0, r0, #(0x1 << 5) ;Enables caching NEON data within the L1 data cache 36*f3782652STreehugger Robot MCR p15, 0, r0, c1, c0, 1 ; Write Auxiliary Control Register 37*f3782652STreehugger Robot 38*f3782652STreehugger Robot;================================================================== 39*f3782652STreehugger Robot; Cortex-A8 program flow prediction 40*f3782652STreehugger Robot;================================================================== 41*f3782652STreehugger Robot 42*f3782652STreehugger Robot MRC p15, 0, r0, c1, c0, 0 ; read CP15 register 1 into r0 43*f3782652STreehugger Robot ORR r0, r0, #(0x1 <<11) ; Enable all forms of branch prediction 44*f3782652STreehugger Robot ;BIC r0, r0, #(0x1 << 11) ; Disable all forms of branch prediction 45*f3782652STreehugger Robot MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1 46*f3782652STreehugger Robot 47*f3782652STreehugger Robot;================================================================== 48*f3782652STreehugger Robot 49*f3782652STreehugger Robot BX lr 50*f3782652STreehugger Robot 51*f3782652STreehugger Robot END ; mark the end of this file 52*f3782652STreehugger Robot 53