1 /*
2 * Copyright (c) 2021-2022 Arm Limited.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24 #include "src/cpu/kernels/CpuDirectConv3dKernel.h"
25
26 #include "arm_compute/core/Error.h"
27 #include "arm_compute/core/Helpers.h"
28 #include "arm_compute/core/IAccessWindow.h"
29 #include "arm_compute/core/ITensor.h"
30 #include "arm_compute/core/Types.h"
31 #include "arm_compute/core/Utils.h"
32 #include "arm_compute/core/Validate.h"
33 #include "arm_compute/core/utils/misc/ShapeCalculator.h"
34 #include "src/core/CPP/Validate.h"
35 #include "src/core/NEON/wrapper/wrapper.h"
36 #include "src/core/common/Registrars.h"
37 #include "src/core/helpers/AutoConfiguration.h"
38 #include "src/cpu/kernels/conv3d/neon/list.h"
39
40 #include <algorithm>
41
42 using namespace arm_compute::detail;
43
44 namespace arm_compute
45 {
46 namespace cpu
47 {
48 namespace kernels
49 {
50 namespace
51 {
52 static const std::vector<CpuDirectConv3dKernel::DirectConv3dKernel> available_kernels =
53 {
54 #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
55 {
56 "neon_fp16_directconv3d",
__anon5309f39b0202() 57 [](const DataTypeISASelectorData & data) { return data.dt == DataType::F16 && data.isa.fp16; },
58 REGISTER_FP16_NEON(arm_compute::cpu::directconv3d_float_neon_ndhwc<float16_t>)
59 },
60 #endif /* !defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) */
61 {
62 "neon_fp32_directconv3d",
__anon5309f39b0302() 63 [](const DataTypeISASelectorData & data) { return data.dt == DataType::F32; },
64 REGISTER_FP32_NEON(arm_compute::cpu::directconv3d_float_neon_ndhwc<float>)
65 },
66 {
67 "neon_qasymm8_directconv3d",
__anon5309f39b0402() 68 [](const DataTypeISASelectorData & data) { return data.dt == DataType::QASYMM8; },
69 REGISTER_QASYMM8_NEON(arm_compute::cpu::directconv3d_quantized_neon_ndhwc<uint8_t>)
70 },
71 {
72 "neon_qasymm8_signed_directconv3d",
__anon5309f39b0502() 73 [](const DataTypeISASelectorData & data) { return data.dt == DataType::QASYMM8_SIGNED; },
74 REGISTER_QASYMM8_SIGNED_NEON(arm_compute::cpu::directconv3d_quantized_neon_ndhwc<int8_t>)
75 }
76 };
77
validate_arguments(const ITensorInfo * src0,const ITensorInfo * src1,const ITensorInfo * src2,const ITensorInfo * dst,const Conv3dInfo & conv_info)78 Status validate_arguments(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, const ITensorInfo *dst, const Conv3dInfo &conv_info)
79 {
80 ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src0, src1, dst);
81 ARM_COMPUTE_RETURN_ERROR_ON(src0->data_layout() != DataLayout::NDHWC);
82 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(src0, src1, dst);
83 ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src0);
84 ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src0, 1, DataType::F16, DataType::F32, DataType::QASYMM8, DataType::QASYMM8_SIGNED);
85 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src0, src1);
86 ARM_COMPUTE_RETURN_ERROR_ON(conv_info.dilation != Size3D(1U, 1U, 1U));
87
88 const auto *uk = CpuDirectConv3dKernel::get_implementation(DataTypeISASelectorData{ src0->data_type(), CPUInfo::get().get_isa() });
89
90 ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr);
91
92 const DataLayout data_layout = src0->data_layout();
93 const int channel_idx = get_data_layout_dimension_index(data_layout, DataLayoutDimension::CHANNEL);
94
95 // Weight layout is D, H, W, Cin, Cout
96 ARM_COMPUTE_RETURN_ERROR_ON(src1->num_dimensions() > 5);
97 ARM_COMPUTE_RETURN_ERROR_ON(src1->dimension(1) != src0->dimension(channel_idx));
98
99 if(src2 != nullptr)
100 {
101 if(is_data_type_quantized(src0->data_type()))
102 {
103 ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src2, 1, DataType::S32);
104 }
105 else
106 {
107 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src1, src2);
108 }
109 ARM_COMPUTE_RETURN_ERROR_ON_MSG(src2->dimension(0) != src1->dimension(0), "Biases size and number of dst feature maps should match");
110 ARM_COMPUTE_RETURN_ERROR_ON_MSG(src2->num_dimensions() > 1, "Biases should be one dimensional");
111 }
112
113 // Checks performed when output is configured
114 if(dst->total_size() != 0)
115 {
116 TensorShape output_shape = misc::shape_calculator::compute_conv3d_shape(src0->tensor_shape(), src1->tensor_shape(), conv_info);
117
118 DataType data_type = src0->data_type();
119
120 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DIMENSIONS(dst->tensor_shape(), output_shape);
121 ARM_COMPUTE_RETURN_ERROR_ON(dst->data_type() != data_type);
122 }
123
124 return Status{};
125 }
126 } // namespace
127
configure(const ITensorInfo * src0,const ITensorInfo * src1,const ITensorInfo * src2,ITensorInfo * dst,const Conv3dInfo & conv_info)128 void CpuDirectConv3dKernel::configure(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, ITensorInfo *dst, const Conv3dInfo &conv_info)
129 {
130 ARM_COMPUTE_UNUSED(src2);
131 ARM_COMPUTE_ERROR_ON_NULLPTR(src0, src1, dst);
132
133 const auto *uk = CpuDirectConv3dKernel::get_implementation(DataTypeISASelectorData{ src0->data_type(), CPUInfo::get().get_isa() });
134
135 ARM_COMPUTE_ERROR_ON_NULLPTR(uk);
136
137 _conv_info = conv_info;
138 _run_method = uk->ukernel;
139 _name = std::string("CpuDirectConv3dKernel").append("/").append(uk->name);
140
141 // Get convolved dimensions
142 TensorShape output_shape = misc::shape_calculator::compute_conv3d_shape(src0->tensor_shape(), src1->tensor_shape(), conv_info);
143
144 DataType data_type = src0->data_type();
145
146 // Output auto inizialitation if not yet initialized
147 auto_init_if_empty(*dst, output_shape, 1, data_type);
148
149 // Perform validation step
150 ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(src0, src1, src2, dst, conv_info));
151
152 // Configure kernel window
153 Window win = calculate_max_window(*dst, Steps());
154 ICpuKernel::configure(win);
155 }
156
validate(const ITensorInfo * src0,const ITensorInfo * src1,const ITensorInfo * src2,const ITensorInfo * dst,const Conv3dInfo & conv_info)157 Status CpuDirectConv3dKernel::validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, const ITensorInfo *dst, const Conv3dInfo &conv_info)
158 {
159 ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(src0, src1, src2, dst, conv_info));
160
161 return Status{};
162 }
163
run_op(ITensorPack & tensors,const Window & window,const ThreadInfo & info)164 void CpuDirectConv3dKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info)
165 {
166 ARM_COMPUTE_UNUSED(info);
167 ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this);
168 ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(ICpuKernel::window(), window);
169 ARM_COMPUTE_ERROR_ON(_run_method == nullptr);
170
171 auto src0 = tensors.get_const_tensor(TensorType::ACL_SRC_0);
172 auto src1 = tensors.get_const_tensor(TensorType::ACL_SRC_1);
173 auto src2 = tensors.get_const_tensor(TensorType::ACL_SRC_2);
174 auto dst = tensors.get_tensor(TensorType::ACL_DST);
175
176 _run_method(src0, src1, src2, dst, _conv_info, window);
177 }
178
name() const179 const char *CpuDirectConv3dKernel::name() const
180 {
181 return _name.c_str();
182 }
183
get_available_kernels()184 const std::vector<CpuDirectConv3dKernel::DirectConv3dKernel> &CpuDirectConv3dKernel::get_available_kernels()
185 {
186 return available_kernels;
187 }
188
189 } // namespace kernels
190 } // namespace cpu
191 } // namespace arm_compute