1 /*
2 * Copyright (c) 2019-2022 Arm Limited.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24 #include "src/cpu/kernels/CpuDepthwiseConv2dNativeKernel.h"
25
26 #include "arm_compute/core/ITensor.h"
27 #include "arm_compute/core/ITensorInfo.h"
28 #include "arm_compute/core/utils/misc/ShapeCalculator.h"
29 #include "src/core/CPP/Validate.h"
30 #include "src/core/NEON/wrapper/traits.h"
31 #include "src/core/common/Registrars.h"
32 #include "src/core/helpers/AutoConfiguration.h"
33 #include "src/core/helpers/WindowHelpers.h"
34 #include "src/cpu/kernels/depthwiseconv2d/list.h"
35 #include "support/ToolchainSupport.h"
36
37 namespace arm_compute
38 {
39 namespace cpu
40 {
41 namespace kernels
42 {
43 namespace
44 {
45 static const std::vector<CpuDepthwiseConv2dNativeKernel::DepthwiseConv2dNativeKernel> available_kernels =
46 {
47 {
48 "neon_qu8_deptwiseconv2dnative",
49 [](const DepthwiseConv2dNativeDataTypeISASelectorData & data)
__anon7a9233130202() 50 {
51 return (data.weights_dt == DataType::QASYMM8);
52 },
53 REGISTER_QASYMM8_NEON(neon_qu8_deptwiseconv2dnative)
54 },
55 {
56 "neon_qs8_deptwiseconv2dnative",
57 [](const DepthwiseConv2dNativeDataTypeISASelectorData & data)
__anon7a9233130302() 58 {
59 return (data.weights_dt == DataType::QASYMM8_SIGNED);
60 },
61 REGISTER_QASYMM8_SIGNED_NEON(neon_qs8_deptwiseconv2dnative)
62 },
63 {
64 "neon_fp16_deptwiseconv2dnative",
65 [](const DepthwiseConv2dNativeDataTypeISASelectorData & data)
__anon7a9233130402() 66 {
67 return (data.weights_dt == DataType::F16 && data.isa.fp16);
68 },
69 REGISTER_FP16_NEON(neon_fp16_deptwiseconv2dnative)
70 },
71 {
72 "neon_fp32_deptwiseconv2dnative",
73 [](const DepthwiseConv2dNativeDataTypeISASelectorData & data)
__anon7a9233130502() 74 {
75 return (data.weights_dt == DataType::F32);
76 },
77 REGISTER_FP32_NEON(neon_fp32_deptwiseconv2dnative)
78 },
79 {
80 "neon_qp8_qu8_deptwiseconv2dnative",
81 [](const DepthwiseConv2dNativeDataTypeISASelectorData & data)
__anon7a9233130602() 82 {
83 return (data.weights_dt == DataType::QSYMM8_PER_CHANNEL && data.source_dt == DataType::QASYMM8);
84 },
85 REGISTER_QASYMM8_NEON(neon_qp8_qu8_deptwiseconv2dnative)
86 },
87 {
88 "neon_qp8_qs8_deptwiseconv2dnative",
89 [](const DepthwiseConv2dNativeDataTypeISASelectorData & data)
__anon7a9233130702() 90 {
91 return (data.weights_dt == DataType::QSYMM8_PER_CHANNEL && data.source_dt != DataType::QASYMM8);
92 },
93 REGISTER_QASYMM8_SIGNED_NEON(neon_qp8_qs8_deptwiseconv2dnative)
94 },
95 };
96
validate_arguments(const ITensorInfo * src,const ITensorInfo * weights,const ITensorInfo * biases,const ITensorInfo * dst,const ConvolutionInfo & info)97 Status validate_arguments(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, const ConvolutionInfo &info)
98 {
99 ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, weights, dst);
100 ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src);
101 ARM_COMPUTE_RETURN_ERROR_ON(src->data_layout() == DataLayout::UNKNOWN);
102 ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::F16, DataType::F32);
103 ARM_COMPUTE_RETURN_ERROR_ON(info.depth_multiplier == 0);
104 ARM_COMPUTE_RETURN_ERROR_ON(weights->dimension(1) + (weights->dimension(1) - 1) * (info.dilation.x() - 1) > src->dimension(1) + info.pad_stride_info.pad_left() + info.pad_stride_info.pad_right());
105 ARM_COMPUTE_RETURN_ERROR_ON(weights->dimension(2) + (weights->dimension(2) - 1) * (info.dilation.y() - 1) > src->dimension(2) + info.pad_stride_info.pad_top() + info.pad_stride_info.pad_bottom());
106 ARM_COMPUTE_RETURN_ERROR_ON((src->dimension(0) * info.depth_multiplier) != weights->dimension(0));
107 ARM_COMPUTE_RETURN_ERROR_ON((info.dilation.x() < 1) || (info.dilation.y() < 1));
108 ARM_COMPUTE_RETURN_ERROR_ON((info.pad_stride_info.stride().first < 1) || (info.pad_stride_info.stride().second < 1));
109
110 if(is_data_type_quantized_per_channel(weights->data_type()))
111 {
112 ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(weights, 1, DataType::QSYMM8_PER_CHANNEL);
113 ARM_COMPUTE_RETURN_ERROR_ON(weights->dimension(0) != weights->quantization_info().scale().size());
114 }
115 else
116 {
117 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, weights);
118 }
119
120 if(biases != nullptr)
121 {
122 ARM_COMPUTE_RETURN_ERROR_ON(biases->num_dimensions() > 1);
123 ARM_COMPUTE_RETURN_ERROR_ON(biases->dimension(0) != weights->dimension(0));
124
125 if(is_data_type_quantized_asymmetric(src->data_type()))
126 {
127 ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(biases, 1, DataType::S32);
128 }
129 else
130 {
131 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(weights, biases);
132 }
133 }
134
135 if(dst->total_size() != 0)
136 {
137 const TensorShape output_shape = misc::shape_calculator::compute_depthwise_convolution_shape(*src, *weights, info);
138 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DIMENSIONS(dst->tensor_shape(), output_shape);
139 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst);
140 }
141
142 return Status{};
143 }
144 } // namespace
145
configure(const ITensorInfo * src,const ITensorInfo * weights,const ITensorInfo * biases,ITensorInfo * dst,const ConvolutionInfo & info)146 void CpuDepthwiseConv2dNativeKernel::configure(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, ITensorInfo *dst, const ConvolutionInfo &info)
147 {
148 ARM_COMPUTE_ERROR_ON_NULLPTR(src, weights, dst);
149 ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(src, weights, (biases != nullptr) ? biases : nullptr, dst, info));
150
151 _has_biases = (biases != nullptr);
152 _conv_info = info;
153
154 const auto uk = CpuDepthwiseConv2dNativeKernel::get_implementation(
155 DepthwiseConv2dNativeDataTypeISASelectorData{ weights->data_type(), src->data_type(), CPUInfo::get().get_isa() });
156 ARM_COMPUTE_ERROR_ON(uk == nullptr || uk->ukernel == nullptr);
157 _func = uk->ukernel;
158
159 const TensorShape output_shape = misc::shape_calculator::compute_depthwise_convolution_shape(*src, *weights, info);
160 auto_init_if_empty(*dst, src->clone()->set_is_resizable(true).reset_padding().set_tensor_shape(output_shape).set_quantization_info(dst->quantization_info()));
161
162 Window win = calculate_max_window(*dst, Steps());
163 ICpuKernel::configure(win);
164 }
165
validate(const ITensorInfo * src,const ITensorInfo * weights,const ITensorInfo * biases,const ITensorInfo * dst,const ConvolutionInfo & info)166 Status CpuDepthwiseConv2dNativeKernel::validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, const ConvolutionInfo &info)
167 {
168 ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(src, weights, biases, dst, info));
169 return Status{};
170 }
171
run_op(ITensorPack & tensors,const Window & window,const ThreadInfo & info)172 void CpuDepthwiseConv2dNativeKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info)
173 {
174 ARM_COMPUTE_UNUSED(info);
175 ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this);
176 ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(ICpuKernel::window(), window);
177 ARM_COMPUTE_ERROR_ON(_func == nullptr);
178
179 const auto src = tensors.get_const_tensor(TensorType::ACL_SRC_0);
180 const auto weights = tensors.get_const_tensor(TensorType::ACL_SRC_1);
181 const auto biases = tensors.get_const_tensor(TensorType::ACL_SRC_2);
182 auto dst = tensors.get_tensor(TensorType::ACL_DST);
183 _func(src, weights, biases, dst, window, _has_biases, _conv_info);
184 }
185
name() const186 const char *CpuDepthwiseConv2dNativeKernel::name() const
187 {
188 return "CpuDepthwiseConv2dNativeKernel";
189 }
190
get_available_kernels()191 const std::vector<CpuDepthwiseConv2dNativeKernel::DepthwiseConv2dNativeKernel> &CpuDepthwiseConv2dNativeKernel::get_available_kernels()
192 {
193 return available_kernels;
194 }
195 } // namespace kernels
196 } // namespace cpu
197 } // namespace arm_compute
198