1package xiangshan.backend.issue 2 3import chisel3._ 4import chisel3.util._ 5import top.ArgParser 6import xiangshan.backend.Bundles.DynInst 7import xiangshan.{Redirect, XSCoreParameters, XSCoreParamsKey} 8 9object MultiWakeupQueueMain extends App { 10 val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args) 11 12 val p = config.alterPartial({ case XSCoreParamsKey => XSCoreParameters() }) 13 14// emitVerilog( 15// new MultiWakeupQueue[DynInst, ValidIO[Redirect]]( 16// new DynInst()(p), 17// ValidIO(new Redirect()(p)), 18// Set(2, 4), 19// (dynInst: DynInst, flush: ValidIO[Redirect], stage: Int) => dynInst.robIdx.needFlush(flush) 20// ), 21// Array("--full-stacktrace", "--target-dir", "build/issue") 22// ) 23} 24