1730cfbc0SXuan Hupackage xiangshan.backend.issue 2730cfbc0SXuan Hu 3730cfbc0SXuan Huimport chipsalliance.rocketchip.config.Parameters 4730cfbc0SXuan Huimport freechips.rocketchip.diplomacy.LazyModule 5730cfbc0SXuan Huimport top.{ArgParser, BaseConfig, Generator} 6730cfbc0SXuan Huimport xiangshan.{XSCoreParameters, XSCoreParamsKey} 7730cfbc0SXuan Hu 8730cfbc0SXuan Huobject IssueQueueMain extends App { 9730cfbc0SXuan Hu override def main(args: Array[String]): Unit = { 10*8a00ff56SXuan Hu val (config, firrtlOpts, firrtlComplier, firtoolOpts) = ArgParser.parse(args) 11*8a00ff56SXuan Hu 12730cfbc0SXuan Hu val backendParams = config(XSCoreParamsKey).backendParams 13730cfbc0SXuan Hu 14730cfbc0SXuan Hu val iqParams: IssueBlockParams = backendParams.intSchdParams.get.issueBlockParams.head 15*8a00ff56SXuan Hu val iq: IssueQueue = LazyModule(new IssueQueue(iqParams)(config)) 16730cfbc0SXuan Hu 17730cfbc0SXuan Hu Generator.execute( 18730cfbc0SXuan Hu firrtlOpts, 19730cfbc0SXuan Hu iq.module, 20*8a00ff56SXuan Hu firrtlComplier, 21*8a00ff56SXuan Hu firtoolOpts 22730cfbc0SXuan Hu ) 23730cfbc0SXuan Hu } 24730cfbc0SXuan Hu 25730cfbc0SXuan Hu} 26