1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import freechips.rocketchip.diplomacy.LazyModule 5import top.{ArgParser, BaseConfig, Generator} 6import xiangshan.backend.regfile.IntPregParams 7import xiangshan.{XSCoreParameters, XSCoreParamsKey, XSTileKey} 8 9object BackendMain extends App { 10 override def main(args: Array[String]): Unit = { 11 val (config, firrtlOpts, firrtlComplier, firtoolOpts) = ArgParser.parse(args) 12 13 val defaultConfig = config.alterPartial({ 14 // Get XSCoreParams and pass it to the "small module" 15 case XSCoreParamsKey => config(XSTileKey).head 16 }) 17 18 val backendParams = defaultConfig(XSCoreParamsKey).backendParams 19 val backend = LazyModule(new Backend(backendParams)(defaultConfig)) 20 21 Generator.execute( 22 firrtlOpts :+ "--full-stacktrace" :+ "--target-dir" :+ "backend", 23 backend.module, 24 firrtlComplier, 25 firtoolOpts 26 ) 27 println("done") 28 } 29} 30 31