1package xiangshan 2 3import chisel3._ 4import chisel3.stage._ 5import chiseltest._ 6import chiseltest.ChiselScalatestTester 7import chiseltest.VerilatorBackendAnnotation 8import chiseltest.simulator.{VerilatorFlags, VerilatorCFlags} 9import org.scalatest.flatspec.AnyFlatSpec 10import org.scalatest.matchers.must.Matchers 11import firrtl.stage.RunFirrtlTransformAnnotation 12import xstransforms.PrintModuleName 13import firrtl.options.TargetDirAnnotation 14import top.ArgParser 15import utility.FileRegisters 16import xiangshan.backend.decode.DecodeUnit 17import xiangshan.backend.regfile.IntPregParams 18 19object DecodeMain extends App { 20 val (config, firrtlOpts, firrtlComplier, firtoolOpts) = ArgParser.parse(args) 21 // //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config) 22 // If Complex Params are needed, wrap it with a Top Module to do dirty works, 23 // and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params" 24 val defaultConfig = config.alterPartial({ 25 // Get XSCoreParams and pass it to the "small module" 26 case XSCoreParamsKey => config(XSTileKey).head.copy( 27 // Example of how to change params 28 intPreg = IntPregParams( 29 numEntries = 64, 30 numRead = Some(14), 31 numWrite = Some(8), 32 ), 33 ) 34 }) 35 (new ChiselStage).execute(args, Seq( 36 ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig) 37 ))) 38// // Generate files when compiling. Used by ChiselDB. 39// FileRegisters.write("./build") 40} 41 42class DecodeUnitTest extends XSTester { 43 behavior of "DecodeUnit" 44 it should "pass" in { 45 test(new DecodeUnit()(config)).withAnnotations(Seq( 46 VerilatorBackendAnnotation, 47 VerilatorFlags(Seq()), 48 WriteVcdAnnotation, 49 TargetDirAnnotation("./build"), 50 RunFirrtlTransformAnnotation(new PrintModuleName) 51 )){ dut => 52 dut.clock.step(10) 53 } 54 } 55}