1package xiangshan 2 3import chisel3._ 4import chisel3.stage.ChiselGeneratorAnnotation 5import chiseltest._ 6import chiseltest.VerilatorBackendAnnotation 7import chiseltest.simulator.VerilatorFlags 8import top.ArgParser 9import xiangshan.backend.decode.DecodeUnit 10import types.ChiselStage 11import xiangshan.test.types._ 12import xiangshan.transforms.PrintModuleName 13 14object DecodeMain extends App { 15 val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args) 16 // //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config) 17 // If Complex Params are needed, wrap it with a Top Module to do dirty works, 18 // and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params" 19 val defaultConfig = config.alterPartial({ 20 // Get XSCoreParams and pass it to the "small module" 21 case XSCoreParamsKey => config(XSTileKey).head.copy( 22 // Example of how to change params 23 IssQueSize = 12 24 ) 25 }) 26 (new ChiselStage).execute(args, Seq( 27 ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig) 28 ))) 29// // Generate files when compiling. Used by ChiselDB. 30// FileRegisters.write("./build") 31} 32 33class DecodeUnitTest extends XSTester { 34 behavior of "DecodeUnit" 35 it should "pass" in { 36 val printModuleNameAnno = chisel3.BuildInfo.version match { 37 case "3.6.0" => Seq(RunFirrtlTransformAnnotation(new PrintModuleName)) 38 case _ => Seq() 39 } 40 41 test(new DecodeUnit()(config)).withAnnotations(Seq( 42 VerilatorBackendAnnotation, 43 VerilatorFlags(Seq()), 44 WriteVcdAnnotation, 45 TargetDirAnnotation("./build") 46 ) ++ printModuleNameAnno){ dut => 47 dut.clock.step(10) 48 } 49 } 50} 51