1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import device.{AXI4MemorySlave, SimJTAG} 23import difftest._ 24import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule} 25import utility.FileRegisters 26import utility.ChiselDB 27import utility.GTimer 28import xiangshan.DebugOptionsKey 29import utility.Constantin 30 31class SimTop(implicit p: Parameters) extends Module { 32 val debugOpts = p(DebugOptionsKey) 33 34 val l_soc = LazyModule(new XSTop()) 35 val soc = Module(l_soc.module) 36 // Don't allow the top-level signals to be optimized out, 37 // so that we can re-use this SimTop for any generated Verilog RTL. 38 dontTouch(soc.io) 39 40 l_soc.module.dma <> 0.U.asTypeOf(l_soc.module.dma) 41 42 val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2)) 43 val simMMIO = Module(l_simMMIO.module) 44 l_simMMIO.io_axi4 <> soc.peripheral 45 46 val l_simAXIMem = AXI4MemorySlave( 47 l_soc.misc.memAXI4SlaveNode, 48 16L * 1024 * 1024 * 1024, 49 useBlackBox = true, 50 dynamicLatency = debugOpts.UseDRAMSim 51 ) 52 val simAXIMem = Module(l_simAXIMem.module) 53 l_simAXIMem.io_axi4 <> soc.memory 54 55 soc.io.clock := clock.asBool 56 soc.io.reset := reset.asAsyncReset 57 soc.io.extIntrs := simMMIO.io.interrupt.intrVec 58 soc.io.sram_config := 0.U 59 soc.io.pll0_lock := true.B 60 soc.io.cacheable_check := DontCare 61 soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U) 62 63 // soc.io.rtc_clock is a div100 of soc.io.clock 64 val rtcClockDiv = 100 65 val rtcTickCycle = rtcClockDiv / 2 66 val rtcCounter = RegInit(0.U(log2Ceil(rtcTickCycle + 1).W)) 67 rtcCounter := Mux(rtcCounter === (rtcTickCycle - 1).U, 0.U, rtcCounter + 1.U) 68 val rtcClock = RegInit(false.B) 69 when (rtcCounter === 0.U) { 70 rtcClock := ~rtcClock 71 } 72 soc.io.rtc_clock := rtcClock 73 74 val success = Wire(Bool()) 75 val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, !reset.asBool, success) 76 soc.io.systemjtag.reset := reset.asAsyncReset 77 soc.io.systemjtag.mfr_id := 0.U(11.W) 78 soc.io.systemjtag.part_number := 0.U(16.W) 79 soc.io.systemjtag.version := 0.U(4.W) 80 81 val io = IO(new Bundle(){ 82 val logCtrl = new LogCtrlIO 83 val perfInfo = new PerfInfoIO 84 val uart = new UARTIO 85 }) 86 87 simMMIO.io.uart <> io.uart 88 89 val timer = if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) GTimer() else WireDefault(0.U(64.W)) 90 val logEnable = 91 if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) 92 (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end) 93 else WireDefault(false.B) 94 val clean = if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) WireDefault(io.perfInfo.clean) else WireDefault(false.B) 95 val dump = if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) WireDefault(io.perfInfo.dump) else WireDefault(false.B) 96 97 dontTouch(timer) 98 dontTouch(logEnable) 99 dontTouch(clean) 100 dontTouch(dump) 101 102 // Check and dispaly all source and sink connections 103 ExcitingUtils.fixConnections() 104 ExcitingUtils.checkAndDisplay() 105} 106 107object SimTop extends App { 108 override def main(args: Array[String]): Unit = { 109 // Keep this the same as TopMain except that SimTop is used here instead of XSTop 110 val (config, firrtlOpts, firrtlComplier, firtoolOpts) = ArgParser.parse(args) 111 112 // tools: init to close dpi-c when in fpga 113 val envInFPGA = config(DebugOptionsKey).FPGAPlatform 114 val enableChiselDB = config(DebugOptionsKey).EnableChiselDB 115 val enableConstantin = config(DebugOptionsKey).EnableConstantin 116 Constantin.init(enableConstantin && !envInFPGA) 117 ChiselDB.init(enableChiselDB && !envInFPGA) 118 119 Generator.execute( 120 firrtlOpts, 121 DisableMonitors(p => new SimTop()(p))(config), 122 firrtlComplier, 123 firtoolOpts 124 ) 125 126 // tools: write cpp files 127 ChiselDB.addToFileRegisters 128 Constantin.addToFileRegisters 129 FileRegisters.write(fileDir = "./build") 130 DifftestModule.finish("XiangShan") 131 } 132} 133