1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package top 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import chisel3.experimental.dataview._ 24import device.{AXI4MemorySlave, SimJTAG} 25import difftest._ 26import freechips.rocketchip.amba.axi4.AXI4Bundle 27import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule} 28import utility.{ChiselDB, Constantin, FileRegisters, GTimer} 29import xiangshan.DebugOptionsKey 30 31class SimTop(implicit p: Parameters) extends Module { 32 val debugOpts = p(DebugOptionsKey) 33 34 val l_soc = LazyModule(new XSTop()) 35 val soc = Module(l_soc.module) 36 // Don't allow the top-level signals to be optimized out, 37 // so that we can re-use this SimTop for any generated Verilog RTL. 38 dontTouch(soc.io) 39 40 l_soc.module.dma.get <> 0.U.asTypeOf(l_soc.module.dma.get) 41 42 val l_simMMIO = LazyModule(new SimMMIO(l_soc.socMisc.get.peripheralNode.in.head._2)) 43 val simMMIO = Module(l_simMMIO.module) 44 l_simMMIO.io_axi4.elements.head._2 <> soc.peripheral.get.viewAs[AXI4Bundle] 45 46 val l_simAXIMem = AXI4MemorySlave( 47 l_soc.misc.memAXI4SlaveNode, 48 16L * 1024 * 1024 * 1024, 49 useBlackBox = true, 50 dynamicLatency = debugOpts.UseDRAMSim 51 ) 52 val simAXIMem = Module(l_simAXIMem.module) 53 l_simAXIMem.io_axi4.elements.head._2 :<>= soc.memory.viewAs[AXI4Bundle].waiveAll 54 55 soc.io.clock := clock.asBool 56 soc.io.reset := (reset.asBool || soc.io.debug_reset).asAsyncReset 57 soc.io.extIntrs := simMMIO.io.interrupt.intrVec 58 soc.io.sram_config := 0.U 59 soc.io.pll0_lock := true.B 60 soc.io.cacheable_check := DontCare 61 soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U) 62 63 // soc.io.rtc_clock is a div100 of soc.io.clock 64 val rtcClockDiv = 100 65 val rtcTickCycle = rtcClockDiv / 2 66 val rtcCounter = RegInit(0.U(log2Ceil(rtcTickCycle + 1).W)) 67 rtcCounter := Mux(rtcCounter === (rtcTickCycle - 1).U, 0.U, rtcCounter + 1.U) 68 val rtcClock = RegInit(false.B) 69 when (rtcCounter === 0.U) { 70 rtcClock := ~rtcClock 71 } 72 soc.io.rtc_clock := rtcClock 73 74 val success = Wire(Bool()) 75 val jtag = Module(new SimJTAG(tickDelay = 3)(p)) 76 jtag.connect(soc.io.systemjtag.jtag, clock, reset.asBool, !reset.asBool, success) 77 soc.io.systemjtag.reset := reset.asAsyncReset 78 soc.io.systemjtag.mfr_id := 0.U(11.W) 79 soc.io.systemjtag.part_number := 0.U(16.W) 80 soc.io.systemjtag.version := 0.U(4.W) 81 82 val difftest = DifftestModule.finish("XiangShan") 83 84 simMMIO.io.uart <> difftest.uart 85 86 val hasPerf = !debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug 87 val hasLog = !debugOpts.FPGAPlatform && debugOpts.EnableDebug 88 val hasPerfLog = hasPerf || hasLog 89 val timer = if (hasPerfLog) GTimer() else WireDefault(0.U(64.W)) 90 val logEnable = if (hasPerfLog) WireDefault(difftest.logCtrl.enable(timer)) else WireDefault(false.B) 91 val clean = if (hasPerf) WireDefault(difftest.perfCtrl.clean) else WireDefault(false.B) 92 val dump = if (hasPerf) WireDefault(difftest.perfCtrl.dump) else WireDefault(false.B) 93 94 dontTouch(timer) 95 dontTouch(logEnable) 96 dontTouch(clean) 97 dontTouch(dump) 98} 99 100object SimTop extends App { 101 // Keep this the same as TopMain except that SimTop is used here instead of XSTop 102 val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args) 103 104 // tools: init to close dpi-c when in fpga 105 val envInFPGA = config(DebugOptionsKey).FPGAPlatform 106 val enableChiselDB = config(DebugOptionsKey).EnableChiselDB 107 val enableConstantin = config(DebugOptionsKey).EnableConstantin 108 Constantin.init(enableConstantin && !envInFPGA) 109 ChiselDB.init(enableChiselDB && !envInFPGA) 110 111 Generator.execute( 112 firrtlOpts, 113 DisableMonitors(p => new SimTop()(p))(config), 114 firtoolOpts 115 ) 116 117 // tools: write cpp files 118 ChiselDB.addToFileRegisters 119 Constantin.addToFileRegisters 120 FileRegisters.write(fileDir = "./build") 121} 122