xref: /XiangShan/src/test/scala/top/SimTop.scala (revision b6a21a24effdf0453ab76aeb322110e6d9f20d36) 
1package top
2
3import chipsalliance.rocketchip.config.{Config, Parameters}
4import chisel3.stage.ChiselGeneratorAnnotation
5import chisel3._
6import device.{AXI4RAMWrapper, UARTIO}
7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
8import utils.GTimer
9import xiangshan.{DebugOptions, DebugOptionsKey, PerfInfoIO}
10
11class LogCtrlIO extends Bundle {
12  val log_begin, log_end = Input(UInt(64.W))
13  val log_level = Input(UInt(64.W)) // a cpp uint
14}
15
16class SimTop(implicit p: Parameters) extends Module {
17  val debugOpts = p(DebugOptionsKey)
18  val useDRAMSim = debugOpts.UseDRAMSim
19
20  val l_soc = LazyModule(new XSTopWithoutDMA())
21  val soc = Module(l_soc.module)
22
23  val l_simMMIO = LazyModule(new SimMMIO(l_soc.peripheralNode.in.head._2))
24  val simMMIO = Module(l_simMMIO.module)
25  l_simMMIO.connectToSoC(l_soc)
26
27  if(!useDRAMSim){
28    val l_simAXIMem = LazyModule(new AXI4RAMWrapper(
29      l_soc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true
30    ))
31    val simAXIMem = Module(l_simAXIMem.module)
32    l_simAXIMem.connectToSoC(l_soc)
33  }
34
35  soc.io.clock := clock.asBool()
36  soc.io.reset := reset.asBool()
37  soc.io.extIntrs := simMMIO.io.interrupt.intrVec
38
39  val io = IO(new Bundle(){
40    val logCtrl = new LogCtrlIO
41    val perfInfo = new PerfInfoIO
42    val uart = new UARTIO
43    val memAXI = if(useDRAMSim) l_soc.memory.cloneType else null
44  })
45
46  simMMIO.io.uart <> io.uart
47
48  if(useDRAMSim){
49    io.memAXI <> l_soc.memory
50  }
51
52  if (debugOpts.EnableDebug || debugOpts.EnablePerfDebug) {
53    val timer = GTimer()
54    val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end)
55    ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
56    ExcitingUtils.addSource(timer, "logTimestamp")
57  }
58
59  if (debugOpts.EnablePerfDebug) {
60    val clean = io.perfInfo.clean
61    val dump = io.perfInfo.dump
62    ExcitingUtils.addSource(clean, "XSPERF_CLEAN")
63    ExcitingUtils.addSource(dump, "XSPERF_DUMP")
64  }
65
66  // Check and dispaly all source and sink connections
67  ExcitingUtils.fixConnections()
68  ExcitingUtils.checkAndDisplay()
69}
70
71object SimTop extends App {
72
73  override def main(args: Array[String]): Unit = {
74    val (config, firrtlOpts) = ArgParser.parse(args, fpga = false)
75    // generate verilog
76    XiangShanStage.execute(
77      firrtlOpts,
78      Seq(
79        ChiselGeneratorAnnotation(() => new SimTop()(config))
80      )
81    )
82  }
83}
84