1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config.{Config, Parameters} 20import chisel3.stage.ChiselGeneratorAnnotation 21import chisel3._ 22import device.{AXI4RAMWrapper, SimJTAG} 23import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule, LazyModuleImp} 24import utils.GTimer 25import xiangshan.{DebugOptions, DebugOptionsKey} 26import chipsalliance.rocketchip.config._ 27import freechips.rocketchip.devices.debug._ 28import difftest._ 29import freechips.rocketchip.util.ElaborationArtefacts 30import top.TopMain.writeOutputFile 31 32class SimTop(implicit p: Parameters) extends Module { 33 val debugOpts = p(DebugOptionsKey) 34 val useDRAMSim = debugOpts.UseDRAMSim 35 36 val l_soc = LazyModule(new XSTop()) 37 val soc = Module(l_soc.module) 38 39 l_soc.module.dma <> 0.U.asTypeOf(l_soc.module.dma) 40 41 val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2)) 42 val simMMIO = Module(l_simMMIO.module) 43 l_simMMIO.io_axi4 <> soc.peripheral 44 45 if(!useDRAMSim){ 46 val l_simAXIMem = LazyModule(new AXI4RAMWrapper( 47 l_soc.misc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true 48 )) 49 val simAXIMem = Module(l_simAXIMem.module) 50 l_simAXIMem.io_axi4 <> soc.memory 51 } 52 53 soc.io.clock := clock.asBool 54 soc.io.reset := reset.asBool 55 soc.io.extIntrs := simMMIO.io.interrupt.intrVec 56 soc.io.sram_config := 0.U 57 soc.io.pll0_lock := true.B 58 soc.io.cacheable_check := DontCare 59 60 val success = Wire(Bool()) 61 val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, ~reset.asBool, success) 62 soc.io.systemjtag.reset := reset 63 soc.io.systemjtag.mfr_id := 0.U(11.W) 64 soc.io.systemjtag.part_number := 0.U(16.W) 65 soc.io.systemjtag.version := 0.U(4.W) 66 67 val io = IO(new Bundle(){ 68 val logCtrl = new LogCtrlIO 69 val perfInfo = new PerfInfoIO 70 val uart = new UARTIO 71 val memAXI = if(useDRAMSim) soc.memory.cloneType else null 72 }) 73 74 simMMIO.io.uart <> io.uart 75 76 if(useDRAMSim){ 77 io.memAXI <> soc.memory 78 } 79 80 if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) { 81 val timer = GTimer() 82 val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end) 83 ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE") 84 ExcitingUtils.addSource(timer, "logTimestamp") 85 } 86 87 if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) { 88 val clean = io.perfInfo.clean 89 val dump = io.perfInfo.dump 90 ExcitingUtils.addSource(clean, "XSPERF_CLEAN") 91 ExcitingUtils.addSource(dump, "XSPERF_DUMP") 92 } 93 94 // Check and dispaly all source and sink connections 95 ExcitingUtils.fixConnections() 96 ExcitingUtils.checkAndDisplay() 97} 98 99object SimTop extends App { 100 override def main(args: Array[String]): Unit = { 101 // Keep this the same as TopMain except that SimTop is used here instead of XSTop 102 val (config, firrtlOpts) = ArgParser.parse(args) 103 XiangShanStage.execute(firrtlOpts, Seq( 104 ChiselGeneratorAnnotation(() => { 105 DisableMonitors(p => new SimTop()(p))(config) 106 }) 107 )) 108 ElaborationArtefacts.files.foreach{ case (extension, contents) => 109 writeOutputFile("./build", s"XSTop.${extension}", contents()) 110 } 111 } 112} 113