1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import device.{AXI4MemorySlave, SimJTAG} 23import difftest._ 24import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule} 25import utility.{ChiselDB, Constantin, FileRegisters, GTimer} 26import xiangshan.DebugOptionsKey 27 28class SimTop(implicit p: Parameters) extends Module { 29 val debugOpts = p(DebugOptionsKey) 30 31 val l_soc = LazyModule(new XSTop()) 32 val soc = Module(l_soc.module) 33 // Don't allow the top-level signals to be optimized out, 34 // so that we can re-use this SimTop for any generated Verilog RTL. 35 dontTouch(soc.io) 36 37 l_soc.module.dma <> 0.U.asTypeOf(l_soc.module.dma) 38 39 val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2)) 40 val simMMIO = Module(l_simMMIO.module) 41 l_simMMIO.io_axi4 <> soc.peripheral 42 43 val l_simAXIMem = AXI4MemorySlave( 44 l_soc.misc.memAXI4SlaveNode, 45 16L * 1024 * 1024 * 1024, 46 useBlackBox = true, 47 dynamicLatency = debugOpts.UseDRAMSim 48 ) 49 val simAXIMem = Module(l_simAXIMem.module) 50 l_simAXIMem.io_axi4.getWrappedValue :<>= soc.memory.waiveAll 51 52 soc.io.clock := clock.asBool 53 soc.io.reset := reset.asAsyncReset 54 soc.io.extIntrs := simMMIO.io.interrupt.intrVec 55 soc.io.sram_config := 0.U 56 soc.io.pll0_lock := true.B 57 soc.io.cacheable_check := DontCare 58 soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U) 59 60 // soc.io.rtc_clock is a div100 of soc.io.clock 61 val rtcClockDiv = 100 62 val rtcTickCycle = rtcClockDiv / 2 63 val rtcCounter = RegInit(0.U(log2Ceil(rtcTickCycle + 1).W)) 64 rtcCounter := Mux(rtcCounter === (rtcTickCycle - 1).U, 0.U, rtcCounter + 1.U) 65 val rtcClock = RegInit(false.B) 66 when (rtcCounter === 0.U) { 67 rtcClock := ~rtcClock 68 } 69 soc.io.rtc_clock := rtcClock 70 71 val success = Wire(Bool()) 72 val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, !reset.asBool, success) 73 soc.io.systemjtag.reset := reset.asAsyncReset 74 soc.io.systemjtag.mfr_id := 0.U(11.W) 75 soc.io.systemjtag.part_number := 0.U(16.W) 76 soc.io.systemjtag.version := 0.U(4.W) 77 78 val io = IO(new Bundle(){ 79 val logCtrl = new LogCtrlIO 80 val perfInfo = new PerfInfoIO 81 val uart = new UARTIO 82 }) 83 84 simMMIO.io.uart <> io.uart 85 86 val timer = if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) GTimer() else WireDefault(0.U(64.W)) 87 val logEnable = 88 if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) 89 (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end) 90 else WireDefault(false.B) 91 val clean = if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) WireDefault(io.perfInfo.clean) else WireDefault(false.B) 92 val dump = if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) WireDefault(io.perfInfo.dump) else WireDefault(false.B) 93 94 dontTouch(timer) 95 dontTouch(logEnable) 96 dontTouch(clean) 97 dontTouch(dump) 98} 99 100object SimTop extends App { 101 // Keep this the same as TopMain except that SimTop is used here instead of XSTop 102 val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args) 103 104 // tools: init to close dpi-c when in fpga 105 val envInFPGA = config(DebugOptionsKey).FPGAPlatform 106 val enableChiselDB = config(DebugOptionsKey).EnableChiselDB 107 val enableConstantin = config(DebugOptionsKey).EnableConstantin 108 Constantin.init(enableConstantin && !envInFPGA) 109 ChiselDB.init(enableChiselDB && !envInFPGA) 110 111 Generator.execute( 112 firrtlOpts, 113 DisableMonitors(p => new SimTop()(p))(config), 114 firtoolOpts 115 ) 116 117 // tools: write cpp files 118 ChiselDB.addToFileRegisters 119 Constantin.addToFileRegisters 120 FileRegisters.write(fileDir = "./build") 121 DifftestModule.finish("XiangShan") 122} 123