xref: /XiangShan/src/test/scala/top/SimTop.scala (revision 1bc48dd1fa0af361fd194c65bad3b86349ec2903) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9*          http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package top
19
20import org.chipsalliance.cde.config.Parameters
21import chisel3._
22import chisel3.util._
23import chisel3.experimental.dataview._
24import device.{AXI4MemorySlave, SimJTAG}
25import difftest._
26import freechips.rocketchip.amba.axi4.AXI4Bundle
27import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule}
28import freechips.rocketchip.util.HeterogeneousBag
29import utility.{ChiselDB, Constantin, FileRegisters, GTimer}
30import xiangshan.DebugOptionsKey
31
32class SimTop(implicit p: Parameters) extends Module {
33  val debugOpts = p(DebugOptionsKey)
34
35  val l_soc = LazyModule(new XSTop())
36  val soc = Module(l_soc.module)
37  // Don't allow the top-level signals to be optimized out,
38  // so that we can re-use this SimTop for any generated Verilog RTL.
39  dontTouch(soc.io)
40
41  if (!l_soc.module.dma.isEmpty) {
42    l_soc.module.dma.get <> WireDefault(0.U.asTypeOf(l_soc.module.dma.get))
43  }
44
45  val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2))
46  val simMMIO = Module(l_simMMIO.module)
47  l_simMMIO.io_axi4.elements.head._2 <> soc.peripheral.viewAs[AXI4Bundle]
48
49  val l_simAXIMem = AXI4MemorySlave(
50    l_soc.misc.memAXI4SlaveNode,
51    16L * 1024 * 1024 * 1024,
52    useBlackBox = true,
53    dynamicLatency = debugOpts.UseDRAMSim
54  )
55  val simAXIMem = Module(l_simAXIMem.module)
56  l_simAXIMem.io_axi4.elements.head._2 :<>= soc.memory.viewAs[AXI4Bundle].waiveAll
57
58  soc.io.clock := clock.asBool
59  soc.io.reset := (reset.asBool || soc.io.debug_reset).asAsyncReset
60  soc.io.extIntrs := simMMIO.io.interrupt.intrVec
61  soc.io.sram_config := 0.U
62  soc.io.pll0_lock := true.B
63  soc.io.cacheable_check := DontCare
64  soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U)
65  l_soc.nmi.foreach(_.foreach(intr => { intr := false.B; dontTouch(intr) }))
66
67  // soc.io.rtc_clock is a div100 of soc.io.clock
68  val rtcClockDiv = 100
69  val rtcTickCycle = rtcClockDiv / 2
70  val rtcCounter = RegInit(0.U(log2Ceil(rtcTickCycle + 1).W))
71  rtcCounter := Mux(rtcCounter === (rtcTickCycle - 1).U, 0.U, rtcCounter + 1.U)
72  val rtcClock = RegInit(false.B)
73  when (rtcCounter === 0.U) {
74    rtcClock := ~rtcClock
75  }
76  soc.io.rtc_clock := rtcClock
77
78  val success = Wire(Bool())
79  val jtag = Module(new SimJTAG(tickDelay = 3)(p))
80  jtag.connect(soc.io.systemjtag.jtag, clock, reset.asBool, !reset.asBool, success)
81  soc.io.systemjtag.reset := reset.asAsyncReset
82  soc.io.systemjtag.mfr_id := 0.U(11.W)
83  soc.io.systemjtag.part_number := 0.U(16.W)
84  soc.io.systemjtag.version := 0.U(4.W)
85
86  val difftest = DifftestModule.finish("XiangShan")
87
88  simMMIO.io.uart <> difftest.uart
89
90  val hasPerf = !debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug
91  val hasLog = !debugOpts.FPGAPlatform && debugOpts.EnableDebug
92  val hasPerfLog = hasPerf || hasLog
93  val timer = if (hasPerfLog) GTimer() else WireDefault(0.U(64.W))
94  val logEnable = if (hasPerfLog) WireDefault(difftest.logCtrl.enable(timer)) else WireDefault(false.B)
95  val clean = if (hasPerf) WireDefault(difftest.perfCtrl.clean) else WireDefault(false.B)
96  val dump = if (hasPerf) WireDefault(difftest.perfCtrl.dump) else WireDefault(false.B)
97
98  dontTouch(timer)
99  dontTouch(logEnable)
100  dontTouch(clean)
101  dontTouch(dump)
102}
103
104object SimTop extends App {
105  // Keep this the same as TopMain except that SimTop is used here instead of XSTop
106  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
107
108  // tools: init to close dpi-c when in fpga
109  val envInFPGA = config(DebugOptionsKey).FPGAPlatform
110  val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
111  val enableConstantin = config(DebugOptionsKey).EnableConstantin
112  Constantin.init(enableConstantin && !envInFPGA)
113  ChiselDB.init(enableChiselDB && !envInFPGA)
114
115  Generator.execute(
116    firrtlOpts,
117    DisableMonitors(p => new SimTop()(p))(config),
118    firtoolOpts
119  )
120
121  // tools: write cpp files
122  ChiselDB.addToFileRegisters
123  Constantin.addToFileRegisters
124  FileRegisters.write(fileDir = "./build")
125}
126