xref: /XiangShan/src/test/scala/top/SimMMIO.scala (revision af5eab6138b2a5ca5ee5cee365e270e37b381c07) 
1package top
2
3import chisel3._
4import chisel3.util._
5
6import bus.simplebus.SimpleBus
7
8class DeviceHelper extends BlackBox {
9  val io = IO(new Bundle {
10    val clk = Input(Clock())
11    val reqValid = Input(Bool())
12    val reqWen = Input(Bool())
13    val reqAddr = Input(UInt(32.W))
14    val reqWdata = Input(UInt(32.W))
15    val respRdata = Output(UInt(32.W))
16  })
17}
18
19class SimMMIO extends Module {
20  val io = IO(new Bundle {
21    val rw = Flipped(new SimpleBus)
22    val mmioTrap = new Bundle {
23      val valid = Output(Bool())
24      val cmd = Output(UInt(3.W))
25      val rdata = Input(UInt(32.W))
26    }
27  })
28
29  val wen = io.rw.isWrite()
30  val wdataVec = VecInit.tabulate(4) { i => io.rw.req.bits.wdata(8 * (i + 1) - 1, 8 * i) }
31  val wmask = VecInit.tabulate(4) { i => io.rw.req.bits.wmask(i).toBool }
32
33  io.mmioTrap.valid := false.B
34  io.mmioTrap.cmd := 0.U
35
36  val helper = Module(new DeviceHelper)
37  helper.io.clk := clock
38  helper.io.reqValid := io.rw.req.valid
39  helper.io.reqWen := wen
40  helper.io.reqAddr := io.rw.req.bits.addr
41  helper.io.reqWdata := io.rw.req.bits.wdata
42  io.rw.resp.bits.rdata := helper.io.respRdata
43
44  io.rw.req.ready := true.B
45  io.rw.resp.valid := io.rw.req.valid
46
47/*
48  when (io.rw.req.valid) {
49    switch (io.rw.req.bits.addr) {
50      is (0x40600008.U) {
51        // read uartlite stat register
52        io.mmioTrap.valid := true.B
53        io.mmioTrap.cmd := 0.U
54      }
55      is (0x4060000c.U) {
56        // read uartlite ctrl register
57        io.mmioTrap.valid := true.B
58        io.mmioTrap.cmd := 0.U
59      }
60      is (0x40600004.U) {
61        io.mmioTrap.valid := true.B
62        io.mmioTrap.cmd := 6.U
63        when (wen) { printf("%c", wdataVec(0)) }
64      }
65      is (0x40700000.U) {
66        // read RTC
67        io.mmioTrap.valid := true.B
68        io.mmioTrap.cmd := 1.U
69      }
70      is (0x40900000.U) {
71        // read key
72        io.mmioTrap.valid := true.B
73        io.mmioTrap.cmd := 2.U
74      }
75      is (0x40800000.U) {
76        // read screen size
77        io.mmioTrap.valid := true.B
78        io.mmioTrap.cmd := 3.U
79      }
80      is (0x40800004.U) {
81        // write vga sync
82        io.mmioTrap.valid := true.B
83        io.mmioTrap.cmd := 4.U
84      }
85    }
86
87    when (io.rw.req.bits.addr >= 0x40000000.U && io.rw.req.bits.addr < 0x40400000.U && wen) {
88      // write to vmem
89      io.mmioTrap.valid := true.B
90      io.mmioTrap.cmd := 5.U
91    }
92  }
93  */
94
95  //io.rw.req.ready := true.B
96  //io.rw.resp.bits.rdata := io.mmioTrap.rdata
97  //io.rw.resp.valid := io.mmioTrap.valid
98
99  //assert(!io.rw.req.valid || io.mmioTrap.valid, "bad addr = 0x%x", io.rw.req.bits.addr)
100}
101